// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

`begin_keywords "1800-2023"

`define ZERO 0

`ifdef ( ZERO )
// ...
`endif
