#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

import vltest_bootstrap

test.scenarios('vlt')
test.top_filename = "t/t_flag_make_cmake.v"

test.compile(
    # Need --no-print-directory so golden file doesn't compare directory names
    verilator_flags2=[
        "--build --MAKEFLAGS --no-print-directory", " --MAKEFLAGS illegal-flag-to-fail-make"
    ],
    # Recursive make breaks the golden compare
    #expect_filename = test.golden_filename
    fails='any')  # make returns exit code 2

test.passes()
