// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2024 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0

program t;
  initial begin
    $write("*-* All Finished *-*\n");
    // No $finish
  end
endprogram
