mirror of https://github.com/zachjs/sv2v.git
122 lines
1.9 KiB
Systemverilog
122 lines
1.9 KiB
Systemverilog
typedef enum {
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A_1, A_2, A_3
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} EnumA;
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typedef enum {
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B_1 = 2, B_2 = 1, B_3 = 3
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} EnumB;
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typedef enum {
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C_1 = 20, C_2 = 0, C_3 = 19
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} EnumC;
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typedef enum {
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D_1 = 'h10, D_2, D_3
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} EnumD;
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typedef enum {
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E_1, E_2 = 'h10, E_3, E_4, E_5 = 'b10, E_6
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} EnumE;
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typedef enum logic {
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F_1, F_2
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} EnumF;
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typedef enum [0:0] {
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G_1, G_2
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} EnumG;
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typedef logic [3:0] Foo_t;
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typedef enum Foo_t {
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H_1 = 'b1, H_2 = 'b0
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} EnumH;
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typedef enum int {
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I_1, I_2
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} EnumI;
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typedef enum int {
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J_1, J_2, J_3
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} EnumJ;
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typedef enum int {
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Z_1, Z_2, Z_3
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} EnumZ;
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`define PRINT(name, val) \
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dummy``name = name``_``val; \
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$display(`"name %h %h %0d %0d`", \
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name``_``val, dummy``name, $bits(name``_``val), $bits(dummy``name));
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module top;
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EnumA dummyA;
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EnumB dummyB;
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EnumC dummyC;
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EnumD dummyD;
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EnumE dummyE;
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EnumF dummyF;
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EnumG dummyG;
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EnumH dummyH;
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EnumI dummyI;
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initial begin
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`PRINT(A, 1)
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`PRINT(A, 2)
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`PRINT(A, 3)
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`PRINT(B, 1)
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`PRINT(B, 2)
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`PRINT(B, 3)
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`PRINT(C, 1)
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`PRINT(C, 2)
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`PRINT(C, 3)
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`PRINT(D, 1)
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`PRINT(D, 2)
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`PRINT(D, 3)
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`PRINT(E, 1)
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`PRINT(E, 2)
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`PRINT(E, 3)
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`PRINT(E, 4)
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`PRINT(E, 5)
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`PRINT(E, 6)
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`PRINT(F, 1)
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`PRINT(F, 2)
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`PRINT(G, 1)
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`PRINT(G, 2)
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`PRINT(H, 1)
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`PRINT(H, 2)
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`PRINT(I, 1)
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`PRINT(I, 2)
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end
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parameter USE_J = 1;
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generate
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if (USE_J) begin
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EnumJ dummyJ;
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initial begin
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`PRINT(J, 1)
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`PRINT(J, 2)
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`PRINT(J, 3)
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end
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end
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else begin
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EnumZ dummyZ;
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initial begin
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`PRINT(Z, 1)
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`PRINT(Z, 2)
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`PRINT(Z, 3)
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end
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end
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endgenerate
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endmodule
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