mirror of https://github.com/zachjs/sv2v.git
87 lines
2.1 KiB
Systemverilog
87 lines
2.1 KiB
Systemverilog
module Example;
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typedef struct packed {
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logic [10:4] a;
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logic [1:3] bx;
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logic [3:1] by;
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logic [3:4][5:7] cw;
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logic [4:3][5:7] cx;
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logic [3:4][7:5] cy;
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logic [4:3][7:5] cz;
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} T;
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T t;
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initial begin
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$monitor("%2d %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b", $time,
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t, t.a, t.bx, t.by,
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t.cw, t.cw[3], t.cw[4],
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t.cx, t.cx[3], t.cx[4],
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t.cy, t.cy[3], t.cy[4],
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t.cz, t.cz[3], t.cz[4]
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);
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#1 t.a = 1;
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#1 t.a[5+:2] = '1;
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#1 t.a[8-:3] = '1;
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#1 t.a[10] = 1;
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#1 t.a[7] = 0;
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#1 t.bx[1+:1] = 1;
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#1 t.bx[1:2] = 1;
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#1 t.bx[3] = 0;
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#1 t.bx[3-:2] = 1;
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#1 t.bx[2] = 0;
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#1 t.by[1+:1] = 1;
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#1 t.by[2:1] = 1;
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#1 t.by[3] = 0;
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#1 t.by[3-:2] = 1;
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#1 t.by[2] = 0;
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#1 t.cw[3][6+:1] = 1;
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#1 t.cw[3][7-:2] = 1;
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#1 t.cw[3][5+:2] = 0;
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#1 t.cw[3][6:7] = 2'b10;
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#1 t.cw[3][6:7] = 2'b01;
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#1 t.cw[3:4] = '1;
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#1 t.cw[4][5] = 0;
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#1 t.cw[4][6:7] = 0;
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#1 t.cw[3+:2] = 6'b010011;
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#1 t.cw[4-:2] = 6'b101011;
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#1 t.cx[3][6+:1] = 1;
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#1 t.cx[3][7-:2] = 1;
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#1 t.cx[3][5+:2] = 0;
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#1 t.cx[3][6:7] = 2'b10;
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#1 t.cx[3][6:7] = 2'b01;
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#1 t.cx[4:3] = '1;
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#1 t.cx[4][5] = 0;
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#1 t.cx[4][6:7] = 0;
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#1 t.cx[3+:2] = 6'b010011;
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#1 t.cx[4-:2] = 6'b101011;
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#1 t.cy[3][6+:1] = 1;
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#1 t.cy[3][7-:2] = 1;
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#1 t.cy[3][5+:2] = 0;
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#1 t.cy[3][7:6] = 2'b10;
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#1 t.cy[3][7:6] = 2'b01;
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#1 t.cy[3:4] = '1;
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#1 t.cy[4][5] = 0;
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#1 t.cy[4][7:6] = 0;
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#1 t.cy[3+:2] = 6'b010011;
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#1 t.cy[4-:2] = 6'b101011;
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#1 t.cz[3][6+:1] = 1;
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#1 t.cz[3][7-:2] = 1;
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#1 t.cz[3][5+:2] = 0;
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#1 t.cz[3][7:6] = 2'b10;
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#1 t.cz[3][7:6] = 2'b01;
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#1 t.cz[4:3] = '1;
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#1 t.cz[4][5] = 0;
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#1 t.cz[4][7:6] = 0;
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#1 t.cz[3+:2] = 6'b010011;
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#1 t.cz[4-:2] = 6'b101011;
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end
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endmodule
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module top;
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endmodule
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