mirror of https://github.com/zachjs/sv2v.git
19 lines
444 B
Verilog
19 lines
444 B
Verilog
module top;
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function log_imp;
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input integer a;
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input integer b;
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log_imp = !a || b;
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endfunction
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function log_eq;
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input integer a;
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input integer b;
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log_eq = !a == !b;
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endfunction
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initial begin : foo
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integer a, b;
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for (a = -2; a <= 2; a = a + 1)
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for (b = -2; b <= 2; b = b + 1)
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$display(log_imp(a, b), log_eq(a, b));
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end
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endmodule
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