mirror of https://github.com/zachjs/sv2v.git
34 lines
1.4 KiB
Systemverilog
34 lines
1.4 KiB
Systemverilog
`define COUNT_ONES(expr) (0 \
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+ ((expr) >> 0 & 1'b1) + ((expr) >> 1 & 1'b1) + ((expr) >> 2 & 1'b1) + ((expr) >> 3 & 1'b1) \
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+ ((expr) >> 4 & 1'b1) + ((expr) >> 5 & 1'b1) + ((expr) >> 6 & 1'b1) + ((expr) >> 7 & 1'b1) \
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+ ((expr) >> 8 & 1'b1) + ((expr) >> 9 & 1'b1) + ((expr) >> 10 & 1'b1) + ((expr) >> 11 & 1'b1) \
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+ ((expr) >> 12 & 1'b1) + ((expr) >> 13 & 1'b1) + ((expr) >> 14 & 1'b1) + ((expr) >> 15 & 1'b1) \
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+ ((expr) >> 16 & 1'b1) + ((expr) >> 17 & 1'b1) + ((expr) >> 18 & 1'b1) + ((expr) >> 19 & 1'b1) \
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+ ((expr) >> 20 & 1'b1) + ((expr) >> 21 & 1'b1) + ((expr) >> 22 & 1'b1) + ((expr) >> 23 & 1'b1) \
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+ ((expr) >> 24 & 1'b1) + ((expr) >> 25 & 1'b1) + ((expr) >> 26 & 1'b1) + ((expr) >> 27 & 1'b1) \
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+ ((expr) >> 28 & 1'b1) + ((expr) >> 29 & 1'b1) + ((expr) >> 30 & 1'b1) + ((expr) >> 31 & 1'b1) \
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)
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module top;
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reg [31:0] data;
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`define TEST(idx, pattern, in_width, out_width) \
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localparam p``idx = pattern; \
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wire [in_width - 1:0] i``idx; \
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wire [out_width - 1:0] o``idx; \
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assign i``idx = data[0+:in_width]; \
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Example #(p``idx, in_width) e``idx(i``idx, o``idx);
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`TEST(1, 5'b10101, 5, 3)
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`TEST(2, 10'b1110001111, 10, 7)
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integer i;
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initial begin
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data = 0;
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for (i = 0; i < 100; i = i + 1) begin
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data = 1664525 * data + 1013904223;
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#1 $display("%b %b %b", data, o1, o2);
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end
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end
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endmodule
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