name: sv2v version: 0.0.1 synopsis: SystemVerilog to Verilog conversion description: A tool for coverting SystemVerilog to Verilog. Originally forked from the Verilog parser found at https://github.com/tomahawkins/verilog category: Language, Hardware, Embedded, Development author: Zachary Snow , Tom Hawkins maintainer: Zachary Snow license: BSD3 license-file: LICENSE homepage: https://github.com/zachjs/sv2v build-type: Simple cabal-version: >= 1.12 executable sv2v default-language: Haskell2010 main-is: sv2v.hs hs-source-dirs: src build-tools: alex >= 3 && < 4, happy >= 1 && < 2 build-depends: array, base, cmdargs, containers, directory, filepath, hashable, mtl other-modules: -- SystemVerilog modules Language.SystemVerilog Language.SystemVerilog.AST Language.SystemVerilog.AST.Attr Language.SystemVerilog.AST.Decl Language.SystemVerilog.AST.Description Language.SystemVerilog.AST.Expr Language.SystemVerilog.AST.GenItem Language.SystemVerilog.AST.LHS Language.SystemVerilog.AST.ModuleItem Language.SystemVerilog.AST.Op Language.SystemVerilog.AST.ShowHelp Language.SystemVerilog.AST.Stmt Language.SystemVerilog.AST.Type Language.SystemVerilog.Parser Language.SystemVerilog.Parser.Lex Language.SystemVerilog.Parser.Parse Language.SystemVerilog.Parser.ParseDecl Language.SystemVerilog.Parser.Tokens -- Conversion modules Convert Convert.AlwaysKW Convert.AsgnOp Convert.Assertion Convert.Bits Convert.Enum Convert.FuncRet Convert.Interface Convert.KWArgs Convert.Logic Convert.NamedBlock Convert.NestPI Convert.Package Convert.PackedArray Convert.Return Convert.StarPort Convert.StmtBlock Convert.Struct Convert.Typedef Convert.Traverse Convert.UnbasedUnsized Convert.Unique -- sv2v CLI modules Job ghc-options: -O3 -threaded -rtsopts -with-rtsopts=-N -funbox-strict-fields -Wall -j source-repository head type: git location: git://github.com/zachjs/sv2v.git