name: sv2v
version: 0.0.1
synopsis: SystemVerilog to Verilog conversion
description:
  A tool for coverting SystemVerilog to Verilog. Originally forked from the
  Verilog parser found at https://github.com/tomahawkins/verilog
category: Language, Hardware, Embedded, Development

author: Zachary Snow <zach@zachjs.com>, Tom Hawkins <tomahawkins@gmail.com>
maintainer: Zachary Snow <zach@zachjs.com>
license: BSD3
license-file: LICENSE
homepage: https://github.com/zachjs/sv2v

build-type: Simple
cabal-version: >= 1.12

executable sv2v
  default-language: Haskell2010
  main-is: sv2v.hs
  hs-source-dirs: src
  build-tools:
    alex  >= 3 && < 4,
    happy >= 1 && < 2
  build-depends:
    array,
    base,
    cmdargs,
    containers,
    mtl
  other-modules:
    -- SystemVerilog modules
    Language.SystemVerilog
    Language.SystemVerilog.AST
    Language.SystemVerilog.Parser
    Language.SystemVerilog.Parser.Lex
    Language.SystemVerilog.Parser.Parse
    Language.SystemVerilog.Parser.Preprocess
    Language.SystemVerilog.Parser.Tokens
    -- Conversion modules
    Convert
    Convert.AlwaysKW
    Convert.CaseKW
    Convert.Logic
    Convert.PackedArray
    Convert.SplitPortDecl
    Convert.StarPort
    Convert.Typedef
    Convert.Traverse
    -- sv2v CLI modules
    Args
  ghc-options:
    -O3
    -threaded
    -rtsopts
    -with-rtsopts=-N
    -funbox-strict-fields
    -Wall

source-repository head
  type:     git
  location: git://github.com/zachjs/sv2v.git