15 Commits

Author	SHA1	Message	Date
Zachary Snow	167c65db11	pass through downstream compiler directives	2019-10-10 20:53:49 -04:00
Zachary Snow	a1735ffef7	fix lexing identifiers and numbers across macro boundaries	2019-10-06 15:16:48 -04:00
Zachary Snow	2ca8a022ad	support and conversion for -> and <->	2019-09-15 13:55:40 -04:00
Zachary Snow	f5d6683422	generalization of array dimension(s) system functions	2019-09-14 12:38:26 -04:00
Zachary Snow	6ddf782383	drop timeunit and timescale (closes #31)	2019-09-11 21:44:57 -04:00
Zachary Snow	33bea9e694	added remaining SV keywords	2019-09-04 21:02:02 -04:00
Zachary Snow	e79c95c5f0	some cleanup throughout the SystemVerilog module	2019-04-03 13:45:43 -04:00
Zachary Snow	c53b39319d	added support and conversion handling of the $bits system function ... This also entailed further fleshing out the expression traversal helper to cover expressions in generate blocks, which could, of course, use $bits.	2019-04-02 00:16:09 -04:00
Zachary Snow	a432d75939	additional SystemVerilog language support ... - unique0 and priority - uniqueness on if statements - preliminary discard-only parsing of assertions - parameters with alias typenames	2019-03-30 00:47:42 -04:00
Zachary Snow	d578aee5d9	conflate the preprocessor and lexer ... This should make it much easier to add support for ``, `", macros with arguments, etc., in the future.	2019-03-29 05:33:17 -04:00
Zachary Snow	e69895af54	initial setup for combining pre-processor and lexer	2019-03-29 01:10:46 -04:00
Zachary Snow	cecd141e57	revamped support system with most SystemVerilog types and signed types	2019-03-22 17:45:31 -04:00
Zachary Snow	acfbdb07f8	completely rewrote preprocessor; more extensive directive support (include, timescale)	2019-03-18 05:00:23 -04:00
Zachary Snow	460c0ee497	broader operator support; other parser cleanup	2019-03-04 18:25:14 -05:00
Zachary Snow	7bc81ef67b	directory re-org; streamline build setup	2019-02-28 13:52:31 -05:00