diff --git a/src/Language/SystemVerilog/Parser/Lex.x b/src/Language/SystemVerilog/Parser/Lex.x
index e3f03e8..7818778 100644
--- a/src/Language/SystemVerilog/Parser/Lex.x
+++ b/src/Language/SystemVerilog/Parser/Lex.x
@@ -540,7 +540,9 @@ lexFile includePaths env path = do
                     (show $ length $ lsSpecStack finalState)
             else
                 Right (finalToks, lsEnv finalState)
-            where finalToks = coalesce $ reverse $ lsToks finalState
+            where
+                finalToks = coalesce $ combineBoundaries $
+                    reverse $ lsToks finalState
     where
         setEnv = do
             modify $ \s -> s
@@ -569,6 +571,12 @@ coalesce (Token t1 str1 pn1 : Token MacroBoundary _ _ : Token t2 str2 pn2 : rest
         immediatelyFollows = apn2 == foldl alexMove apn1 str1
 coalesce (x : xs) = x : coalesce xs
 
+combineBoundaries :: [Token] -> [Token]
+combineBoundaries [] = []
+combineBoundaries (Token MacroBoundary s p : Token MacroBoundary _ _ : rest) =
+    combineBoundaries $ Token MacroBoundary s p : rest
+combineBoundaries (x : xs) = x : combineBoundaries xs
+
 -- invoked by alexMonadScan
 alexEOF :: Alex ()
 alexEOF = return ()
diff --git a/test/lex/macro_boundary.sv b/test/lex/macro_boundary.sv
index d4daa1f..dd7ef36 100644
--- a/test/lex/macro_boundary.sv
+++ b/test/lex/macro_boundary.sv
@@ -1,5 +1,7 @@
 `define SIZE 4
+`define NESTED_SIZE `SIZE
 `define NAME op
 module t`NAME;
     initial $display(`SIZE'ha);
+    initial $display(`NESTED_SIZE'ha);
 endmodule