From fb2f3005eb6c5c088c75bdb30594d38a99552a25 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Mon, 31 Jul 2023 22:58:32 -0400
Subject: [PATCH] undoing some minor stylistic changes

---
 src/Language/SystemVerilog/Parser/Parse.y | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index e1fb325..4226b38 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -694,15 +694,16 @@ ModuleItems :: { [ModuleItem] }
   : {- empty -}                    { [] }
   | ";" ModuleItems                { $2 }
   | MITrace ModuleItem ModuleItems { addMITrace $1 ($2 ++ $3) }
+
 ModuleItem :: { [ModuleItem] }
-  : NonGenerateModuleItem           { $1 }
+  : NonGenerateModuleItem { $1 }
   | AttributeInstance ModuleItem    { map (addMIAttr $1) $2 }
   | "generate" GenItems endgenerate { [Generate $2] }
 NonGenerateModuleItemA :: { [ModuleItem] }
   : NonGenerateModuleItem                    { $1 }
   | AttributeInstance NonGenerateModuleItemA { map (addMIAttr $1) $2 }
--- This item covers module instantiations and all declarations
 NonGenerateModuleItem :: { [ModuleItem] }
+  -- This item covers module instantiations and all declarations
   : ModuleDeclTokens(";")                {% mapM recordPartUsed $ parseDTsAsModuleItems $1 }
   | ParameterDecl(";")                   { map (MIPackageItem . Decl) $1 }
   | "defparam" LHSAsgns ";"              { map (uncurry Defparam) $2 }
@@ -1450,7 +1451,7 @@ GenItems :: { [GenItem] }
   | GenItems GenItem { $1 ++ [$2] }
 
 GenItem :: { GenItem }
-  : MITrace GenBlock               { uncurry GenBlock $2 }
+  : MITrace GenBlock              { uncurry GenBlock $2 }
   | MITrace NonGenerateModuleItemA { genItemsToGenItem $ map GenModuleItem $ addMITrace $1 $2 }
 ConditionalGenerateConstruct :: { GenItem }
   : "if" "(" Expr ")" GenItemOrNull "else" GenItemOrNull { GenIf $3 $5 $7      }