diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y index 2d5f157..862d9c7 100644 --- a/src/Language/SystemVerilog/Parser/Parse.y +++ b/src/Language/SystemVerilog/Parser/Parse.y @@ -731,8 +731,9 @@ PackageItem :: { [PackageItem] } | NonDeclPackageItem { $1 } NonDeclPackageItem :: { [PackageItem] } : "typedef" Type Identifier ";" { [Typedef $2 $3] } - | "function" opt(Lifetime) FuncRetAndName TFItems DeclsAndStmts "endfunction" opt(Tag) { [Function $2 (fst $3) (snd $3) (map defaultFuncInput $ (map makeInput $4) ++ fst $5) (snd $5)] } - | "task" opt(Lifetime) Identifier TFItems DeclsAndStmts "endtask" opt(Tag) { [Task $2 $3 (map defaultFuncInput $ $4 ++ fst $5) (snd $5)] } + | "function" opt(Lifetime) FuncRetAndName TFItems DeclsAndStmts "endfunction" opt(Tag) { [Function $2 (fst $3) (snd $3) (map defaultFuncInput $ (map makeInput $4) ++ fst $5) (snd $5)] } + | "function" opt(Lifetime) "void" Identifier TFItems DeclsAndStmts "endfunction" opt(Tag) { [Task $2 $4 (map defaultFuncInput $ $5 ++ fst $6) (snd $6)] } + | "task" opt(Lifetime) Identifier TFItems DeclsAndStmts "endtask" opt(Tag) { [Task $2 $3 (map defaultFuncInput $ $4 ++ fst $5) (snd $5)] } | "import" PackageImportItems ";" { map (uncurry Import) $2 } | "export" PackageImportItems ";" { map (Export . Just) $2 } | "export" "*" "::" "*" ";" { [Export Nothing] } -- "Nothing" being no restrictions diff --git a/test/basic/function_void.sv b/test/basic/function_void.sv new file mode 100644 index 0000000..fdc21f4 --- /dev/null +++ b/test/basic/function_void.sv @@ -0,0 +1,6 @@ +module top; + function void foo; + $display("foo called"); + endfunction + initial foo; +endmodule diff --git a/test/basic/function_void.v b/test/basic/function_void.v new file mode 100644 index 0000000..5e66980 --- /dev/null +++ b/test/basic/function_void.v @@ -0,0 +1,6 @@ +module top; + task foo; + $display("foo called"); + endtask + initial foo; +endmodule