From f71accb3c8aa48f584189867a204da4a67d3f223 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Sun, 9 May 2021 18:06:46 -0400
Subject: [PATCH] fix simple delayed multi-pack conversion within interface

---
 src/Convert/ImplicitNet.hs      |  3 ++-
 src/Convert/MultiplePacked.hs   |  9 +++++++--
 test/basic/interface_delay_1.sv | 15 +++++++++++++++
 test/basic/interface_delay_1.v  |  8 ++++++++
 4 files changed, 32 insertions(+), 3 deletions(-)
 create mode 100644 test/basic/interface_delay_1.sv
 create mode 100644 test/basic/interface_delay_1.v

diff --git a/src/Convert/ImplicitNet.hs b/src/Convert/ImplicitNet.hs
index 9af144f..7fa765e 100644
--- a/src/Convert/ImplicitNet.hs
+++ b/src/Convert/ImplicitNet.hs
@@ -61,7 +61,8 @@ traverseModuleItemM defaultNetType (orig @ (NOutputGate _ _ x lhss expr)) = do
     _ <- mapM (needsLHS defaultNetType) lhss
     needsExpr defaultNetType expr
     return orig
-traverseModuleItemM defaultNetType (orig @ (Instance _ _ _ _ ports)) = do
+traverseModuleItemM defaultNetType (orig @ (Instance _ _ x _ ports)) = do
+    insertElem x ()
     _ <- mapM (needsExpr defaultNetType . snd) ports
     return orig
 traverseModuleItemM _ item = return item
diff --git a/src/Convert/MultiplePacked.hs b/src/Convert/MultiplePacked.hs
index 969696e..b8f403b 100644
--- a/src/Convert/MultiplePacked.hs
+++ b/src/Convert/MultiplePacked.hs
@@ -39,8 +39,13 @@ import Language.SystemVerilog.AST
 type TypeInfo = (Type, [Range])
 
 convert :: [AST] -> [AST]
-convert = map $ traverseDescriptions $ partScoper
-    traverseDeclM traverseModuleItemM traverseGenItemM traverseStmtM
+convert = map $ traverseDescriptions convertDescription
+
+convertDescription :: Description -> Description
+convertDescription (description @ (Part _ _ Module _ _ _ _)) =
+    partScoper traverseDeclM traverseModuleItemM traverseGenItemM traverseStmtM
+    description
+convertDescription other = other
 
 -- collects and converts declarations with multiple packed dimensions
 traverseDeclM :: Decl -> Scoper TypeInfo Decl
diff --git a/test/basic/interface_delay_1.sv b/test/basic/interface_delay_1.sv
new file mode 100644
index 0000000..b6148c4
--- /dev/null
+++ b/test/basic/interface_delay_1.sv
@@ -0,0 +1,15 @@
+interface Interface;
+    logic [0:1][0:2] arr;
+endinterface
+
+module Module(intf);
+    Interface intf;
+endmodule
+
+module top;
+    Interface intf();
+    Module mod [1][2] (intf);
+    assign intf.arr[1] = 6;
+    assign intf.arr[0][0] = 1;
+    initial $display("%b", intf.arr);
+endmodule
diff --git a/test/basic/interface_delay_1.v b/test/basic/interface_delay_1.v
new file mode 100644
index 0000000..bb338f4
--- /dev/null
+++ b/test/basic/interface_delay_1.v
@@ -0,0 +1,8 @@
+module top;
+    if (1) begin : intf
+        wire [0:1][0:2] arr;
+    end
+    assign intf.arr[1] = 6;
+    assign intf.arr[0][0] = 1;
+    initial $display("%b", intf.arr);
+endmodule