From eebe41427e230d1211fbd07b59bd07395f8244b4 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Thu, 31 Oct 2019 20:39:11 -0400 Subject: [PATCH] language support for final blocks --- src/Convert/Jump.hs | 7 +++++++ src/Convert/Logic.hs | 2 ++ src/Convert/Traverse.hs | 8 +++++++- src/Language/SystemVerilog/AST/ModuleItem.hs | 2 ++ src/Language/SystemVerilog/Parser/Parse.y | 1 + 5 files changed, 19 insertions(+), 1 deletion(-) diff --git a/src/Convert/Jump.hs b/src/Convert/Jump.hs index 5daba8c..3db2d53 100644 --- a/src/Convert/Jump.hs +++ b/src/Convert/Jump.hs @@ -60,6 +60,13 @@ convertModuleItem (Initial stmt) = where initialState = Info { sJumpType = JTNone, sLoopID = "" } (stmt', finalState) = runState (convertStmt stmt) initialState +convertModuleItem (Final stmt) = + if sJumpType finalState == JTNone + then Final stmt' + else error "illegal jump statement within final construct" + where + initialState = Info { sJumpType = JTNone, sLoopID = "" } + (stmt', finalState) = runState (convertStmt stmt) initialState convertModuleItem (AlwaysC kw stmt) = if sJumpType finalState == JTNone then AlwaysC kw stmt' diff --git a/src/Convert/Logic.hs b/src/Convert/Logic.hs index 226a4fd..9eddf2d 100644 --- a/src/Convert/Logic.hs +++ b/src/Convert/Logic.hs @@ -144,6 +144,8 @@ regIdents (AlwaysC _ stmt) = removeTimings other = other regIdents (Initial stmt) = regIdents $ AlwaysC Always stmt +regIdents (Final stmt) = + regIdents $ AlwaysC Always stmt regIdents _ = return () lhsIdents :: LHS -> Writer Idents () diff --git a/src/Convert/Traverse.hs b/src/Convert/Traverse.hs index 284d97e..28fbd7f 100644 --- a/src/Convert/Traverse.hs +++ b/src/Convert/Traverse.hs @@ -199,6 +199,8 @@ traverseStmtsM' strat mapper = moduleItemMapper return $ MIPackageItem $ Task lifetime name decls stmts' moduleItemMapper (Initial stmt) = fullMapper stmt >>= return . Initial + moduleItemMapper (Final stmt) = + fullMapper stmt >>= return . Final moduleItemMapper other = return $ other fullMapper = traverseNestedStmtsM mapper @@ -577,6 +579,8 @@ traverseExprsM' strat exprMapper = moduleItemMapper stmtMapper stmt >>= return . AlwaysC kw moduleItemMapper (Initial stmt) = stmtMapper stmt >>= return . Initial + moduleItemMapper (Final stmt) = + stmtMapper stmt >>= return . Final moduleItemMapper (Assign delay lhs expr) = do delay' <- maybeExprMapper delay lhs' <- lhsMapper lhs @@ -1034,7 +1038,7 @@ collectNestedExprsM :: Monad m => CollectorM m Expr -> CollectorM m Expr collectNestedExprsM = collectify traverseNestedExprsM -- Traverse all the declaration scopes within a ModuleItem. Note that Functions, --- Tasks, Always and Initial blocks are all NOT passed through ModuleItem +-- Tasks, Always/Initial/Final blocks are all NOT passed through ModuleItem -- mapper, and Decl ModuleItems are NOT passed through the Decl mapper. The -- state is restored to its previous value after each scope is exited. Only the -- Decl mapper may modify the state, as we maintain the invariant that all other @@ -1082,6 +1086,8 @@ traverseScopesM declMapper moduleItemMapper stmtMapper = fullStmtMapper stmt >>= return . AlwaysC kw redirectModuleItem (Initial stmt) = fullStmtMapper stmt >>= return . Initial + redirectModuleItem (Final stmt) = + fullStmtMapper stmt >>= return . Final redirectModuleItem item = moduleItemMapper item diff --git a/src/Language/SystemVerilog/AST/ModuleItem.hs b/src/Language/SystemVerilog/AST/ModuleItem.hs index f574ecf..13a4183 100644 --- a/src/Language/SystemVerilog/AST/ModuleItem.hs +++ b/src/Language/SystemVerilog/AST/ModuleItem.hs @@ -41,6 +41,7 @@ data ModuleItem | Generate [GenItem] | Modport Identifier [ModportDecl] | Initial Stmt + | Final Stmt | MIPackageItem PackageItem | NInputGate NInputGateKW (Maybe Identifier) LHS [Expr] | NOutputGate NOutputGateKW (Maybe Identifier) [LHS] Expr @@ -56,6 +57,7 @@ instance Show ModuleItem where show (Generate b ) = printf "generate\n%s\nendgenerate" (indent $ unlines' $ map show b) show (Modport x l) = printf "modport %s(\n%s\n);" x (indent $ intercalate ",\n" $ map showModportDecl l) show (Initial s ) = printf "initial %s" (show s) + show (Final s ) = printf "final %s" (show s) show (NInputGate kw x lhs exprs) = printf "%s%s (%s, %s);" (show kw) (maybe "" (" " ++) x) (show lhs) (commas $ map show exprs) show (NOutputGate kw x lhss expr) = printf "%s%s (%s, %s);" (show kw) (maybe "" (" " ++) x) (commas $ map show lhss) (show expr) show (Assign d a b) = diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y index 7796e2d..be842e1 100644 --- a/src/Language/SystemVerilog/Parser/Parse.y +++ b/src/Language/SystemVerilog/Parser/Parse.y @@ -649,6 +649,7 @@ NonGenerateModuleItem :: { [ModuleItem] } | "assign" opt(DelayControl) LHSAsgns ";" { map (uncurry $ Assign $2) $3 } | AlwaysKW Stmt { [AlwaysC $1 $2] } | "initial" Stmt { [Initial $2] } + | "final" Stmt { [Final $2] } | "genvar" Identifiers ";" { map Genvar $2 } | "modport" ModportItems ";" { map (uncurry Modport) $2 } | NonDeclPackageItem { map MIPackageItem $1 }