diff --git a/src/Language/SystemVerilog/AST/Expr.hs b/src/Language/SystemVerilog/AST/Expr.hs index 5764f4e..692abbd 100644 --- a/src/Language/SystemVerilog/AST/Expr.hs +++ b/src/Language/SystemVerilog/AST/Expr.hs @@ -47,7 +47,7 @@ instance Show Expr where show (Repeat e l ) = printf "{%s {%s}}" (show e) (commas $ map show l) show (Concat l ) = printf "{%s}" (commas $ map show l) show (UniOp a b ) = printf "(%s %s)" (show a) (show b) - show (BinOp a o b) = printf "(%s %s %s)" (show a) (show o) (show b) + show (BinOp o a b) = printf "(%s %s %s)" (show a) (show o) (show b) show (Cast t e ) = printf "%s'(%s)" (show t) (show e) show (Dot e n ) = printf "%s.%s" (show e) n show (Mux c a b) = printf "(%s ? %s : %s)" (show c) (show a) (show b) diff --git a/src/Language/SystemVerilog/AST/Stmt.hs b/src/Language/SystemVerilog/AST/Stmt.hs index fbfab13..b151d4d 100644 --- a/src/Language/SystemVerilog/AST/Stmt.hs +++ b/src/Language/SystemVerilog/AST/Stmt.hs @@ -41,11 +41,11 @@ data Stmt instance Show Stmt where show (Block name decls stmts) = - printf "begin%s\n%s\n%s\nend" header (block decls) (block stmts) + printf "begin%s\n%s\nend" header body where header = maybe "" (" : " ++) name - block :: Show t => [t] -> String - block = indent . unlines' . map show + bodyLines = (map show decls) ++ (map show stmts) + body = indent $ unlines' bodyLines show (Case u kw e cs def) = printf "%s%s (%s)\n%s%s\nendcase" uniqStr (show kw) (show e) bodyStr defStr where @@ -66,7 +66,7 @@ instance Show Stmt where show (If a b Null) = printf "if (%s) %s" (show a) (show b) show (If a b c ) = printf "if (%s) %s\nelse %s" (show a) (show b) (show c) show (Return e ) = printf "return %s;" (show e) - show (Timing t s ) = printf "%s%s" (show t) (show s) + show (Timing t s ) = printf "%s %s" (show t) (show s) show (Null ) = ";" data CaseKW