From e8ed885f2c744d16f99456a9ff213016eabb1f8a Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Thu, 7 Mar 2019 01:38:42 -0500 Subject: [PATCH] support for single-expr implicit dimensions --- src/Language/SystemVerilog/Parser/Parse.y | 7 +++++-- src/Language/SystemVerilog/Parser/ParseDecl.hs | 12 +++++++++--- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y index 85104bd..e93eb34 100644 --- a/src/Language/SystemVerilog/Parser/Parse.y +++ b/src/Language/SystemVerilog/Parser/Parse.y @@ -355,8 +355,11 @@ Dimensions :: { [Range] } : {- empty -} { [] } | DimensionsNonEmpty { $1 } DimensionsNonEmpty :: { [Range] } - : Range { [$1] } - | DimensionsNonEmpty Range { $1 ++ [$2] } + : Dimension { [$1] } + | DimensionsNonEmpty Dimension { $1 ++ [$2] } +Dimension :: { Range } + : Range { $1 } + | "[" Expr "]" { (simplify $ BinOp Sub $2 (Number "1"), Number "0") } DeclAsgns :: { [(Identifier, Expr)] } : DeclAsgn { [$1] } diff --git a/src/Language/SystemVerilog/Parser/ParseDecl.hs b/src/Language/SystemVerilog/Parser/ParseDecl.hs index 2939e0d..5d84589 100644 --- a/src/Language/SystemVerilog/Parser/ParseDecl.hs +++ b/src/Language/SystemVerilog/Parser/ParseDecl.hs @@ -239,9 +239,15 @@ takeType (DTIdent tn : rest) = (Alias tn, rest) takeType rest = (Implicit, rest) takeRanges :: [DeclToken] -> ([Range], [DeclToken]) -takeRanges (DTRange r : rest) = (r : rs, rest') - where (rs, rest') = takeRanges rest -takeRanges rest = ([], rest) +takeRanges [] = ([], []) +takeRanges (token : tokens) = + case token of + DTRange r -> (r : rs, rest ) + DTBit s -> (asRange s : rs, rest ) + _ -> ([] , token : tokens) + where + (rs, rest) = takeRanges tokens + asRange s = (simplify $ BinOp Sub s (Number "1"), Number "0") -- TODO: entrypoints besides `parseDTsAsDeclOrAsgn` should disallow `DTAsgnNBlk` -- Note: matching DTAsgnNBlk too is a bit of a hack to allow for tripLookahead