From e80f880f4318fa3dab7993383c7c9d7ea02075b9 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Fri, 30 Aug 2019 20:34:56 -0400 Subject: [PATCH] additional expression simplification special cases --- src/Language/SystemVerilog/AST/Expr.hs | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/Language/SystemVerilog/AST/Expr.hs b/src/Language/SystemVerilog/AST/Expr.hs index 6db0719..20383c5 100644 --- a/src/Language/SystemVerilog/AST/Expr.hs +++ b/src/Language/SystemVerilog/AST/Expr.hs @@ -142,6 +142,18 @@ simplify (Mux (BinOp Ge c1 c2) e1 e2) = e1' = simplify e1 e2' = simplify e2 nochange = Mux (BinOp Ge c1' c2') e1' e2' +simplify (BinOp Sub (Number n1) (BinOp Sub (Number n2) e)) = + simplify $ BinOp Add (BinOp Sub (Number n1) (Number n2)) e +simplify (BinOp Sub (Number n1) (BinOp Sub e (Number n2))) = + simplify $ BinOp Sub (BinOp Add (Number n1) (Number n2)) e +simplify (BinOp Add (BinOp Sub (Number n1) e) (Number n2)) = + case (readNumber n1, readNumber n2) of + (Just x, Just y) -> + simplify $ BinOp Sub (Number $ show (x + y)) e' + _ -> nochange + where + e' = simplify e + nochange = BinOp Add (BinOp Sub (Number n1) e') (Number n2) simplify (BinOp op e1 e2) = case (op, e1', e2') of (Add, Number "0", e) -> e