From e6e96b622b28ef07132cce27b685a00ede013938 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Wed, 16 Feb 2022 12:01:58 +0100 Subject: [PATCH] support for edge event --- CHANGELOG.md | 1 + src/Convert.hs | 2 ++ src/Convert/SenseEdge.hs | 37 +++++++++++++++++++++++ src/Convert/Traverse.hs | 1 + src/Language/SystemVerilog/AST/Stmt.hs | 2 ++ src/Language/SystemVerilog/Parser/Parse.y | 12 +++++--- sv2v.cabal | 1 + test/core/edge.sv | 8 +++++ test/core/edge.v | 8 +++++ test/core/edge_tb.v | 9 ++++++ 10 files changed, 76 insertions(+), 5 deletions(-) create mode 100644 src/Convert/SenseEdge.hs create mode 100644 test/core/edge.sv create mode 100644 test/core/edge.v create mode 100644 test/core/edge_tb.v diff --git a/CHANGELOG.md b/CHANGELOG.md index 4caf7d3..368f222 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -5,6 +5,7 @@ * Added support for excluding the conversion of unbased unsized literals (e.g., `'1`, `'x`) via `--exclude UnbasedUniszed` * Added support for enumerated type ranges (e.g., `enum { X[3:5] }`) +* Added support for the SystemVerilog `edge` event * Added support for passing through DPI imports and exports * Added support for passing through functions with output ports diff --git a/src/Convert.hs b/src/Convert.hs index 75623ff..4629b38 100644 --- a/src/Convert.hs +++ b/src/Convert.hs @@ -41,6 +41,7 @@ import qualified Convert.ParamType import qualified Convert.PortDecl import qualified Convert.RemoveComments import qualified Convert.ResolveBindings +import qualified Convert.SenseEdge import qualified Convert.Simplify import qualified Convert.Stream import qualified Convert.StringParam @@ -101,6 +102,7 @@ initialPhases selectExclude = , Convert.Jump.convert , Convert.KWArgs.convert , Convert.Unique.convert + , Convert.SenseEdge.convert , Convert.LogOp.convert , Convert.EmptyArgs.convert , Convert.Foreach.convert diff --git a/src/Convert/SenseEdge.hs b/src/Convert/SenseEdge.hs new file mode 100644 index 0000000..ac0a7a8 --- /dev/null +++ b/src/Convert/SenseEdge.hs @@ -0,0 +1,37 @@ +{- sv2v + - Author: Zachary Snow + - + - Conversion for `edge` sensitivity + - + - IEEE 1800-2017 Section 9.4.2 defines `edge` as either `posedge` or `negedge`. + - This does not convert senses in assertions as they are likely either removed + - or fully supported downstream. + -} + +module Convert.SenseEdge (convert) where + +import Convert.Traverse +import Language.SystemVerilog.AST + +convert :: [AST] -> [AST] +convert = + map $ traverseDescriptions $ traverseModuleItems $ traverseStmts $ + traverseNestedStmts convertStmt + +convertStmt :: Stmt -> Stmt +convertStmt (Asgn op (Just timing) lhs expr) = + Asgn op (Just $ convertTiming timing) lhs expr +convertStmt (Timing timing stmt) = + Timing (convertTiming timing) stmt +convertStmt other = other + +convertTiming :: Timing -> Timing +convertTiming (Event sense) = Event $ convertSense sense +convertTiming other = other + +convertSense :: Sense -> Sense +convertSense (SenseOr s1 s2) = + SenseOr (convertSense s1) (convertSense s2) +convertSense (SenseEdge lhs) = + SenseOr (SensePosedge lhs) (SenseNegedge lhs) +convertSense other = other diff --git a/src/Convert/Traverse.hs b/src/Convert/Traverse.hs index de78ac3..e77bea3 100644 --- a/src/Convert/Traverse.hs +++ b/src/Convert/Traverse.hs @@ -386,6 +386,7 @@ traverseStmtLHSsM mapper = stmtMapper senseMapper (Sense lhs) = fullMapper lhs >>= return . Sense senseMapper (SensePosedge lhs) = fullMapper lhs >>= return . SensePosedge senseMapper (SenseNegedge lhs) = fullMapper lhs >>= return . SenseNegedge + senseMapper (SenseEdge lhs) = fullMapper lhs >>= return . SenseEdge senseMapper (SenseOr s1 s2) = do s1' <- senseMapper s1 s2' <- senseMapper s2 diff --git a/src/Language/SystemVerilog/AST/Stmt.hs b/src/Language/SystemVerilog/AST/Stmt.hs index b4c1acc..52086a3 100644 --- a/src/Language/SystemVerilog/AST/Stmt.hs +++ b/src/Language/SystemVerilog/AST/Stmt.hs @@ -175,6 +175,7 @@ data Sense | SenseOr Sense Sense | SensePosedge LHS | SenseNegedge LHS + | SenseEdge LHS | SenseStar deriving Eq @@ -183,6 +184,7 @@ instance Show Sense where show (SenseOr a b) = printf "%s or %s" (show a) (show b) show (SensePosedge a ) = printf "posedge %s" (show a) show (SenseNegedge a ) = printf "negedge %s" (show a) + show (SenseEdge a ) = printf "edge %s" (show a) show (SenseStar ) = "*" data ActionBlock diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y index f77d6a7..46bde32 100644 --- a/src/Language/SystemVerilog/Parser/Parse.y +++ b/src/Language/SystemVerilog/Parser/Parse.y @@ -1233,11 +1233,13 @@ Senses :: { Sense } | Senses "," Sense { SenseOr $1 $3 } Sense :: { Sense } : "(" Sense ")" { $2 } - | LHS { Sense $1 } - | "posedge" LHS { SensePosedge $2 } - | "negedge" LHS { SenseNegedge $2 } - | "posedge" "(" LHS ")" { SensePosedge $3 } - | "negedge" "(" LHS ")" { SenseNegedge $3 } + | LHS { Sense $1 } + | "posedge" LHSOptParen { SensePosedge $2 } + | "negedge" LHSOptParen { SenseNegedge $2 } + | "edge" LHSOptParen { SenseEdge $2 } +LHSOptParen :: { LHS } + : LHS { $1 } + | "(" LHS ")" { $2 } CaseKW :: { CaseKW } : "case" { CaseN } diff --git a/sv2v.cabal b/sv2v.cabal index 3bfb3cf..6e524d8 100644 --- a/sv2v.cabal +++ b/sv2v.cabal @@ -94,6 +94,7 @@ executable sv2v Convert.RemoveComments Convert.ResolveBindings Convert.Scoper + Convert.SenseEdge Convert.Simplify Convert.Stream Convert.StringParam diff --git a/test/core/edge.sv b/test/core/edge.sv new file mode 100644 index 0000000..43db63b --- /dev/null +++ b/test/core/edge.sv @@ -0,0 +1,8 @@ +module mod(input clk); + always @(posedge clk) + $display($time, "posedge"); + always @(negedge clk) + $display($time, "negedge"); + always @(edge clk) + $display($time, "edge"); +endmodule diff --git a/test/core/edge.v b/test/core/edge.v new file mode 100644 index 0000000..157cc23 --- /dev/null +++ b/test/core/edge.v @@ -0,0 +1,8 @@ +module mod(input clk); + always @(posedge clk) + $display($time, "posedge"); + always @(negedge clk) + $display($time, "negedge"); + always @(posedge clk or negedge clk) + $display($time, "edge"); +endmodule diff --git a/test/core/edge_tb.v b/test/core/edge_tb.v new file mode 100644 index 0000000..d25b54d --- /dev/null +++ b/test/core/edge_tb.v @@ -0,0 +1,9 @@ +module top; + reg clk; + initial begin + clk = 0; + repeat (10) + #5 clk = ~clk; + end + mod m(clk); +endmodule