From e4efb4803b0d0cb7bdcf5bc5bd63813a66cbb246 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Wed, 27 Mar 2019 03:33:28 -0400
Subject: [PATCH] fix broken for inits parsing; beefed up relong test script to
 catch such mistakes

---
 .../SystemVerilog/Parser/ParseDecl.hs         | 16 +++++++++++-----
 test/relong/run.sh                            | 19 +++++++++++++++++--
 2 files changed, 28 insertions(+), 7 deletions(-)

diff --git a/src/Language/SystemVerilog/Parser/ParseDecl.hs b/src/Language/SystemVerilog/Parser/ParseDecl.hs
index 1f2fbd0..078212d 100644
--- a/src/Language/SystemVerilog/Parser/ParseDecl.hs
+++ b/src/Language/SystemVerilog/Parser/ParseDecl.hs
@@ -195,13 +195,16 @@ parseDTsAsDeclOrAsgn tokens =
 parseDTsAsDeclsAndAsgns :: [DeclToken] -> [Either Decl (LHS, Expr)]
 parseDTsAsDeclsAndAsgns [] = []
 parseDTsAsDeclsAndAsgns tokens =
-    if hasLeadingAsgn
+    if hasLeadingAsgn || tripLookahead tokens
         then
-            let (lhsToks, l0) = break isAsgnToken tokens
+            let (lhsToks, l0) = break isDTAsgn tokens
                 lhs = takeLHS lhsToks
-                DTAsgnNBlk Nothing expr : l1 = l0
-                DTComma : remaining = l1
-            in Right (lhs, expr) : parseDTsAsDeclsAndAsgns remaining
+                DTAsgn AsgnOpEq expr : l1 = l0
+                asgn = Right (lhs, expr)
+            in case l1 of
+                DTComma : remaining -> asgn : parseDTsAsDeclsAndAsgns remaining
+                [] -> [asgn]
+                _ -> error $ "bad decls and asgns tokens: " ++ show tokens
         else
             let (component, remaining) = parseDTsAsComponent tokens
                 decls = finalize component
@@ -213,6 +216,9 @@ parseDTsAsDeclsAndAsgns tokens =
                 (Just a, Just b) -> a > b
                 (Nothing, Just _) -> True
                 _ -> False
+        isDTAsgn :: DeclToken -> Bool
+        isDTAsgn (DTAsgn _ _) = True
+        isDTAsgn _ = False
 
 isAsgnToken :: DeclToken -> Bool
 isAsgnToken (DTBit             _) = True
diff --git a/test/relong/run.sh b/test/relong/run.sh
index 0297457..086c2dd 100755
--- a/test/relong/run.sh
+++ b/test/relong/run.sh
@@ -1,5 +1,7 @@
 #!/bin/sh
 
+SV2V=../../bin/sv2v
+
 assertExists() {
     file=$1
     [ -f "$file" ]
@@ -28,6 +30,15 @@ simulate() {
     sed -i.orig -e "1,3d" "$sim_outfile"
 }
 
+assertConverts() {
+    ac_file="$1"
+    ac_temp="$SHUNIT_TMPDIR/ac-conv-temp.v"
+    $SV2V "$ac_file" 2> /dev/null > "$ac_temp"
+    assertTrue "1st conversion of $ac_file failed" $?
+    $SV2V "$ac_temp" 2> /dev/null > /dev/null
+    assertTrue "2nd conversion of $ac_file failed" $?
+}
+
 runTest() {
     test=$1
     assertNotNull "test not specified" $test
@@ -38,11 +49,15 @@ runTest() {
 
     assertExists $sv
     assertExists $ve
-    assertExists $sv
+    assertExists $tb
+
+    assertConverts "$sv"
+    assertConverts "$ve"
+    assertConverts "$tb"
 
     # convert the SystemVerilog source file
     cv="$SHUNIT_TMPDIR/conv-$test.v"
-    ../../bin/sv2v $sv 2> /dev/null > $cv
+    $SV2V $sv 2> /dev/null > $cv
     assertTrue "conversion failed" $?
     assertExists $cv