diff --git a/src/Convert/PackedArray.hs b/src/Convert/PackedArray.hs
index ff62d7d..80d5d7e 100644
--- a/src/Convert/PackedArray.hs
+++ b/src/Convert/PackedArray.hs
@@ -90,9 +90,9 @@ recordSeqUsage i = modify $ \s -> s { sSeqUses = Set.insert i $ sSeqUses s }
 recordIdxUsage :: Identifier -> State Info ()
 recordIdxUsage i = modify $ \s -> s { sIdxUses = Set.insert i $ sIdxUses s }
 collectExpr :: Expr -> State Info ()
-collectExpr (Ident      i  ) = recordSeqUsage i
-collectExpr (IdentRange i _) = recordSeqUsage i
-collectExpr (IdentBit   i _) = recordIdxUsage i
+collectExpr (Ident        i   ) = recordSeqUsage i
+collectExpr (Range (Ident i) _) = recordSeqUsage i
+collectExpr (Bit   (Ident i) _) = recordIdxUsage i
 collectExpr _ = return ()
 collectLHS :: LHS -> State Info ()
 collectLHS (LHSIdent  i) = recordSeqUsage i
@@ -165,8 +165,8 @@ unflattener writeToFlatVariant arr (t, (majorHi, majorLo)) =
                     (BinOp Mul (Ident index) size))
             , GenModuleItem $ (uncurry Assign) $
                 if not writeToFlatVariant
-                    then (LHSBit (LHSIdent arrUnflat) $ Ident index, IdentRange arr origRange)
-                    else (LHSRange (LHSIdent arr) origRange, IdentBit arrUnflat $ Ident index)
+                    then (LHSBit (LHSIdent arrUnflat) $ Ident index, Range (Ident arr) origRange)
+                    else (LHSRange (LHSIdent arr) origRange, Bit (Ident arrUnflat) (Ident index))
             ]
         ]
     where
@@ -240,12 +240,12 @@ rewriteModuleItem info =
         rewriteAsgnIdent = rewriteIdent True
 
         rewriteExpr :: Expr -> Expr
-        rewriteExpr (Ident      i)   = Ident    (rewriteReadIdent i)
-        rewriteExpr (IdentBit   i e) = IdentBit (rewriteReadIdent i) e
-        rewriteExpr (IdentRange i (r @ (s, e))) =
+        rewriteExpr (Ident i)= Ident (rewriteReadIdent i)
+        rewriteExpr (Bit   (Ident i) e) = Bit (Ident $ rewriteReadIdent i) e
+        rewriteExpr (Range (Ident i) (r @ (s, e))) =
             if Map.member i typeDims
-                then IdentRange i r'
-                else IdentRange i r
+                then Range (Ident i) r'
+                else Range (Ident i) r
             where
                 (a, b) = head $ snd $ typeRanges $ fst $ typeDims Map.! i
                 size = BinOp Add (BinOp Sub a b) (Number "1")
diff --git a/src/Convert/Traverse.hs b/src/Convert/Traverse.hs
index b3138a8..10d58de 100644
--- a/src/Convert/Traverse.hs
+++ b/src/Convert/Traverse.hs
@@ -160,12 +160,15 @@ traverseNestedExprsM mapper = exprMapper
         em (Number     s) = return $ Number    s
         em (ConstBool  b) = return $ ConstBool b
         em (Ident      i) = return $ Ident     i
-        em (IdentRange i (e1, e2)) = do
+        em (Range e (e1, e2)) = do
+            e' <- exprMapper e
             e1' <- exprMapper e1
             e2' <- exprMapper e2
-            return $ IdentRange i (e1', e2')
-        em (IdentBit   i e) =
-            exprMapper e >>= return . IdentBit i
+            return $ Range e' (e1', e2')
+        em (Bit   e1 e2) = do
+            e1' <- exprMapper e1
+            e2' <- exprMapper e2
+            return $ Bit e1' e2'
         em (Repeat     e l) = do
             e' <- exprMapper e
             l' <- mapM exprMapper l
@@ -185,16 +188,14 @@ traverseNestedExprsM mapper = exprMapper
             e2' <- exprMapper e2
             e3' <- exprMapper e3
             return $ Mux e1' e2' e3'
-        em (Bit        e n) =
-            exprMapper e >>= \e' -> return $ Bit e' n
         em (Cast       t e) =
             exprMapper e >>= return . Cast t
-        em (StructAccess e x) =
-            exprMapper e >>= \e' -> return $ StructAccess e' x
-        em (StructPattern l) = do
+        em (Access e x) =
+            exprMapper e >>= \e' -> return $ Access e' x
+        em (Pattern l) = do
             let names = map fst l
             exprs <- mapM exprMapper $ map snd l
-            return $ StructPattern $ zip names exprs
+            return $ Pattern $ zip names exprs
 
 
 traverseExprsM :: Monad m => MapperM m Expr -> MapperM m ModuleItem
diff --git a/src/Language/SystemVerilog/AST.hs b/src/Language/SystemVerilog/AST.hs
index b151ff1..bfcb082 100644
--- a/src/Language/SystemVerilog/AST.hs
+++ b/src/Language/SystemVerilog/AST.hs
@@ -240,18 +240,17 @@ data Expr
   | Number     String
   | ConstBool  Bool
   | Ident      Identifier
-  | IdentRange Identifier Range
-  | IdentBit   Identifier Expr
+  | Range      Expr Range
+  | Bit        Expr Expr
   | Repeat     Expr [Expr]
   | Concat     [Expr]
   | Call       Identifier [Expr]
   | UniOp      UniOp Expr
   | BinOp      BinOp Expr Expr
   | Mux        Expr Expr Expr
-  | Bit        Expr Int
   | Cast       Type Expr
-  | StructAccess Expr Identifier
-  | StructPattern [(Maybe Identifier, Expr)]
+  | Access     Expr Identifier
+  | Pattern    [(Maybe Identifier, Expr)]
   deriving (Eq, Ord)
 
 data UniOp
@@ -331,18 +330,17 @@ instance Show Expr where
     Number     a        -> a
     ConstBool  a        -> printf "1'b%s" (if a then "1" else "0")
     Ident      a        -> a
-    IdentBit   a b      -> printf "%s[%s]"    a (show b)
-    IdentRange a (b, c) -> printf "%s[%s:%s]" a (show b) (show c)
+    Bit        a b      -> printf "%s[%s]"    (show a) (show b)
+    Range      a (b, c) -> printf "%s[%s:%s]" (show a) (show b) (show c)
     Repeat     a b      -> printf "{%s {%s}}" (show a) (commas $ map show b)
     Concat     a        -> printf "{%s}" (commas $ map show a)
     Call       a b      -> printf "%s(%s)" a (commas $ map show b)
     UniOp      a b      -> printf "(%s %s)" (show a) (show b)
     BinOp      a b c    -> printf "(%s %s %s)" (show b) (show a) (show c)
     Mux        a b c    -> printf "(%s ? %s : %s)" (show a) (show b) (show c)
-    Bit        a b      -> printf "(%s [%d])" (show a) b
     Cast       a b      -> printf "%s'(%s)" (show a) (show b)
-    StructAccess e n    -> printf "%s.%s" (show e) n
-    StructPattern l     -> printf "'{\n%s\n}" (showPatternItems l)
+    Access     e n      -> printf "%s.%s" (show e) n
+    Pattern    l        -> printf "'{\n%s\n}" (showPatternItems l)
     where
       showPatternItems :: [(Maybe Identifier, Expr)] -> String
       showPatternItems l = indent $ intercalate ",\n" (map showPatternItem l)
diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index 519b418..5017459 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -168,7 +168,7 @@ string             { Token Lit_string    _ _ }
 %left  "+" "-"
 %left  "*" "/" "%"
 %left  UPlus UMinus "!" "~" RedOps
-%left  "."
+%left  "(" ")" "[" "]" "."
 
 
 %%
@@ -459,8 +459,8 @@ Expr :: { Expr }
 | Number                      { Number $1 }
 | Identifier "(" CallArgs ")" { Call $1 $3 }
 | Identifier                  { Ident      $1    }
-| Identifier Range            { IdentRange $1 $2 }
-| Identifier "[" Expr "]"     { IdentBit   $1 $3 }
+| Expr Range                  { Range $1 $2 }
+| Expr "[" Expr "]"           { Bit   $1 $3 }
 | "{" Expr "{" Exprs "}" "}"  { Repeat $2 $4 }
 | "{" Exprs "}"               { Concat $2 }
 | Expr "?" Expr ":" Expr      { Mux $1 $3 $5 }
@@ -495,9 +495,10 @@ Expr :: { Expr }
 | "^"  Expr %prec RedOps      { UniOp RedXor  $2 }
 | "~^" Expr %prec RedOps      { UniOp RedXnor $2 }
 | "^~" Expr %prec RedOps      { UniOp RedXnor $2 }
-| Type "'" "(" Expr ")"       { Cast $1 $4 }
-| Expr "." Identifier         { StructAccess $1 $3 }
-| "'" "{" PatternItems "}"    { StructPattern $3 }
+| PartialType "'" "(" Expr ")" { Cast ($1       []) $4 }
+| Identifier  "'" "(" Expr ")" { Cast (Alias $1 []) $4 }
+| Expr "." Identifier         { Access $1 $3 }
+| "'" "{" PatternItems "}"    { Pattern $3 }
 
 PatternItems :: { [(Maybe Identifier, Expr)] }
   : PatternNamedItems   { map (\(x,e) -> (Just x, e)) $1 }