From df4244d8d521299e29812fe06fbb2f764c54d7cb Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Sun, 9 Feb 2020 19:56:28 -0500 Subject: [PATCH] more aggressive expression simplification --- src/Convert/Simplify.hs | 2 ++ src/Language/SystemVerilog/AST/Expr.hs | 1 + 2 files changed, 3 insertions(+) diff --git a/src/Convert/Simplify.hs b/src/Convert/Simplify.hs index 3ee62b4..09f044f 100644 --- a/src/Convert/Simplify.hs +++ b/src/Convert/Simplify.hs @@ -73,6 +73,8 @@ convertExpr info (Mux cc aa bb) = after = simplify before convertExpr _ (other @ Repeat{}) = traverseNestedExprs simplify other convertExpr _ (other @ Concat{}) = simplify other +convertExpr _ (other @ BinOp{}) = simplify other +convertExpr _ (other @ UniOp{}) = simplify other convertExpr _ other = other substitute :: Info -> Expr -> Expr diff --git a/src/Language/SystemVerilog/AST/Expr.hs b/src/Language/SystemVerilog/AST/Expr.hs index 7ebd74c..9a0f5cc 100644 --- a/src/Language/SystemVerilog/AST/Expr.hs +++ b/src/Language/SystemVerilog/AST/Expr.hs @@ -171,6 +171,7 @@ readNumber n = readMaybe n' :: Maybe Int where n' = case n of + '3' : '2' : '\'' : 'd' : rest -> rest '\'' : 'd' : rest -> rest _ -> n