diff --git a/src/Convert/Simplify.hs b/src/Convert/Simplify.hs
index 3ee62b4..09f044f 100644
--- a/src/Convert/Simplify.hs
+++ b/src/Convert/Simplify.hs
@@ -73,6 +73,8 @@ convertExpr info (Mux cc aa bb) =
         after = simplify before
 convertExpr _ (other @ Repeat{}) = traverseNestedExprs simplify other
 convertExpr _ (other @ Concat{}) = simplify other
+convertExpr _ (other @ BinOp{}) = simplify other
+convertExpr _ (other @ UniOp{}) = simplify other
 convertExpr _ other = other
 
 substitute :: Info -> Expr -> Expr
diff --git a/src/Language/SystemVerilog/AST/Expr.hs b/src/Language/SystemVerilog/AST/Expr.hs
index 7ebd74c..9a0f5cc 100644
--- a/src/Language/SystemVerilog/AST/Expr.hs
+++ b/src/Language/SystemVerilog/AST/Expr.hs
@@ -171,6 +171,7 @@ readNumber n =
     readMaybe n' :: Maybe Int
     where
         n' = case n of
+            '3' : '2' : '\'' : 'd' : rest -> rest
             '\'' : 'd' : rest -> rest
             _ -> n