From dd951740e75fc9a4cb8cec23687f73340eda8f2c Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Fri, 16 Jul 2021 12:30:35 -0400
Subject: [PATCH] remove some dead code

---
 src/Convert/FuncRet.hs                    |  1 -
 src/Convert/TFBlock.hs                    |  8 ++------
 src/Language/SystemVerilog/AST/Decl.hs    |  5 +----
 src/Language/SystemVerilog/AST/Expr.hs    |  1 -
 src/Language/SystemVerilog/AST/GenItem.hs | 16 +++-------------
 src/Language/SystemVerilog/AST/Stmt.hs    |  5 +----
 6 files changed, 7 insertions(+), 29 deletions(-)

diff --git a/src/Convert/FuncRet.hs b/src/Convert/FuncRet.hs
index 79a64de..350b413 100644
--- a/src/Convert/FuncRet.hs
+++ b/src/Convert/FuncRet.hs
@@ -21,6 +21,5 @@ convertFunction (MIPackageItem (Function ml t f decls stmts)) =
     where
         t' = case t of
             IntegerVector TReg   sg rs -> Implicit sg rs
-            IntegerVector TLogic sg rs -> Implicit sg rs
             _ -> t
 convertFunction other = other
diff --git a/src/Convert/TFBlock.hs b/src/Convert/TFBlock.hs
index 2ea34d3..463641e 100644
--- a/src/Convert/TFBlock.hs
+++ b/src/Convert/TFBlock.hs
@@ -8,7 +8,7 @@
 
 module Convert.TFBlock (convert) where
 
-import Data.List (intersect, isPrefixOf)
+import Data.List (intersect)
 
 import Convert.Traverse
 import Language.SystemVerilog.AST
@@ -53,7 +53,7 @@ flattenOuterBlocks (Block Seq "" declsA (Block Seq name declsB stmtsA : stmtsB))
                 Block Seq name (declsA ++ declsB) (stmtsA ++ stmtsB)
         else (declsA, Block Seq name declsB stmtsA : stmtsB)
 flattenOuterBlocks (Block Seq name decls stmts)
-    | notscope name = (decls, stmts)
+    | null name = (decls, stmts)
     | otherwise = ([], [Block Seq name decls stmts])
 flattenOuterBlocks stmt = ([], [stmt])
 
@@ -72,7 +72,3 @@ declName (Net  _ _ _ _ x _ _) = x
 declName (Param _ _ x _) = x
 declName (ParamType _ x _) = x
 declName CommentDecl{} = ""
-
-notscope :: Identifier -> Bool
-notscope "" = True
-notscope name = "sv2v_autoblock_" `isPrefixOf` name
diff --git a/src/Language/SystemVerilog/AST/Decl.hs b/src/Language/SystemVerilog/AST/Decl.hs
index eab7256..1c5ed49 100644
--- a/src/Language/SystemVerilog/AST/Decl.hs
+++ b/src/Language/SystemVerilog/AST/Decl.hs
@@ -37,10 +37,7 @@ instance Show Decl where
         where tStr = if t == UnknownType then "" else  " = " ++ show t
     show (Variable d t x a e) = printf "%s%s%s%s%s;" (showPad d) (showPad t) x (showRanges a) (showAssignment e)
     show (Net  d n s t x a e) = printf "%s%s%s %s%s%s%s;" (showPad d) (show n) (showPadBefore s) (showPad t) x (showRanges a) (showAssignment e)
-    show (CommentDecl c) =
-        if elem '\n' c
-            then "// " ++ show c
-            else "// " ++ c
+    show (CommentDecl c) = "// " ++ c
 
 data Direction
     = Input
diff --git a/src/Language/SystemVerilog/AST/Expr.hs b/src/Language/SystemVerilog/AST/Expr.hs
index 517b5e3..18bd98e 100644
--- a/src/Language/SystemVerilog/AST/Expr.hs
+++ b/src/Language/SystemVerilog/AST/Expr.hs
@@ -199,6 +199,5 @@ showParams :: [ParamBinding] -> String
 showParams params = indentedParenList $ map showParam params
 
 showParam :: ParamBinding -> String
-showParam ("*", Right Nil) = ".*"
 showParam ("", arg) = showEither arg
 showParam (i, arg) = printf ".%s(%s)" i (showEither arg)
diff --git a/src/Language/SystemVerilog/AST/GenItem.hs b/src/Language/SystemVerilog/AST/GenItem.hs
index 6f82ba4..930af6a 100644
--- a/src/Language/SystemVerilog/AST/GenItem.hs
+++ b/src/Language/SystemVerilog/AST/GenItem.hs
@@ -42,7 +42,7 @@ instance Show GenItem where
             x1 (show e1)
             (show c)
             x2 (show o2) (show e2)
-            (if s == GenNull then "begin end" else showBareBlock s)
+            (showBareBlock s)
     show (GenNull) = ";"
     show (GenModuleItem item) = show item
 
@@ -54,18 +54,8 @@ showBareBlock (GenBlock x i) =
 showBareBlock item = show item
 
 showBlockedBranch :: GenItem -> String
-showBlockedBranch genItem =
-    showBareBlock $
-    if isControl genItem
-        then GenBlock "" [genItem]
-        else genItem
-    where
-        isControl :: GenItem -> Bool
-        isControl GenIf{} = True
-        isControl GenFor{} = True
-        isControl GenCase{} = True
-        isControl GenModuleItem{} = True
-        isControl _ = False
+showBlockedBranch genItem@GenBlock{} = showBareBlock genItem
+showBlockedBranch genItem = showBareBlock $ GenBlock "" [genItem]
 
 type GenCase = ([Expr], GenItem)
 
diff --git a/src/Language/SystemVerilog/AST/Stmt.hs b/src/Language/SystemVerilog/AST/Stmt.hs
index 2601102..c2da990 100644
--- a/src/Language/SystemVerilog/AST/Stmt.hs
+++ b/src/Language/SystemVerilog/AST/Stmt.hs
@@ -98,10 +98,7 @@ instance Show Stmt where
     show (Continue     ) = "continue;"
     show (Break        ) = "break;"
     show (Null         ) = ";"
-    show (CommentStmt c) =
-        if elem '\n' c
-            then "// " ++ show c
-            else "// " ++ c
+    show (CommentStmt c) = "// " ++ c
 
 showAssign :: (LHS, AsgnOp, Expr) -> String
 showAssign (l, op, e) = (showPad l) ++ (showPad op) ++ (show e)