diff --git a/src/Language/SystemVerilog/AST/Expr.hs b/src/Language/SystemVerilog/AST/Expr.hs
index 69995bd..16165cf 100644
--- a/src/Language/SystemVerilog/AST/Expr.hs
+++ b/src/Language/SystemVerilog/AST/Expr.hs
@@ -73,7 +73,7 @@ instance Show Args where
         where
             strs = (map showPnArg pnArgs) ++ (map showKwArg kwArgs)
             showPnArg = maybe "" show
-            showKwArg (x, me) = printf ".%s(%s)" (show x) (showPnArg me)
+            showKwArg (x, me) = printf ".%s(%s)" x (showPnArg me)
 
 showAssignment :: Maybe Expr -> String
 showAssignment Nothing = ""
diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index 3e946fd..a98aee4 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -568,8 +568,8 @@ TFItems :: { [Decl] }
   |                     ";" { [] }
 
 ParamType :: { Type }
-  : "integer" Signing  { IntegerAtom TInteger $2 }
-  | "integer"          { IntegerAtom TInteger Unspecified }
+  : PartialType         Dimensions { $1 Unspecified $2 }
+  | PartialType Signing Dimensions { $1 $2 $3 }
   | DimensionsNonEmpty { Implicit Unspecified $1 }
   | Signing Dimensions { Implicit $1          $2 }