diff --git a/src/Convert.hs b/src/Convert.hs
index 92f0dfc..ba902c6 100644
--- a/src/Convert.hs
+++ b/src/Convert.hs
@@ -13,6 +13,7 @@ import qualified Convert.AlwaysKW
 import qualified Convert.AsgnOp
 import qualified Convert.Assertion
 import qualified Convert.Bits
+import qualified Convert.BlockDecl
 import qualified Convert.EmptyArgs
 import qualified Convert.Enum
 import qualified Convert.ForDecl
@@ -43,6 +44,7 @@ phases excludes =
     , Convert.NamedBlock.convert
     , Convert.Assertion.convert
     , Convert.Bits.convert
+    , Convert.BlockDecl.convert
     , selectExclude (Job.Logic    , Convert.Logic.convert)
     , Convert.ForDecl.convert
     , Convert.FuncRet.convert
diff --git a/src/Convert/BlockDecl.hs b/src/Convert/BlockDecl.hs
new file mode 100644
index 0000000..5769686
--- /dev/null
+++ b/src/Convert/BlockDecl.hs
@@ -0,0 +1,38 @@
+{- sv2v
+ - Author: Zachary Snow <zach@zachjs.com>
+ -
+ - Verilog-2005 forbids block declarations with default values. We convert
+ - these assignments to separate statements. If we handle static lifetimes in
+ - the future, this conversion may have to change.
+ -}
+
+module Convert.BlockDecl (convert) where
+
+import Data.Maybe (mapMaybe)
+
+import Convert.Traverse
+import Language.SystemVerilog.AST
+
+convert :: [AST] -> [AST]
+convert =
+    map
+    $ traverseDescriptions $ traverseModuleItems
+    $ traverseStmts $ convertStmt
+
+convertStmt :: Stmt -> Stmt
+convertStmt (Block name decls stmts) =
+    Block name decls' stmts'
+    where
+        splitDecls = map splitDecl decls
+        decls' = map fst splitDecls
+        asgns = map asgnStmt $ mapMaybe snd splitDecls
+        stmts' = asgns ++ stmts
+convertStmt other = other
+
+splitDecl :: Decl -> (Decl, Maybe (LHS, Expr))
+splitDecl (Variable d t ident a (Just e)) =
+    (Variable d t ident a Nothing, Just (LHSIdent ident, e))
+splitDecl other = (other, Nothing)
+
+asgnStmt :: (LHS, Expr) -> Stmt
+asgnStmt = uncurry $ AsgnBlk AsgnOpEq
diff --git a/sv2v.cabal b/sv2v.cabal
index fde3a54..89bb68d 100644
--- a/sv2v.cabal
+++ b/sv2v.cabal
@@ -57,6 +57,7 @@ executable sv2v
     Convert.AsgnOp
     Convert.Assertion
     Convert.Bits
+    Convert.BlockDecl
     Convert.EmptyArgs
     Convert.Enum
     Convert.ForDecl
diff --git a/test/basic/for_decl.sv b/test/basic/for_decl.sv
index fe0e1ca..55a54dd 100644
--- a/test/basic/for_decl.sv
+++ b/test/basic/for_decl.sv
@@ -34,4 +34,19 @@ module top;
         end
     end
 
+    initial begin
+        integer i = 0;
+        for (; i < 32; i++)
+            $display("6: ", ~a[i]);
+    end
+
+    initial begin
+        integer j = 0, k;
+        for (; j < 4; j++) begin
+            k = 0;
+            for (; k < 8; k++)
+                $display("7: ", ~a[j * 8 + k] + 11);
+        end
+    end
+
 endmodule
diff --git a/test/basic/for_decl.v b/test/basic/for_decl.v
index d4bf1fc..c67df2b 100644
--- a/test/basic/for_decl.v
+++ b/test/basic/for_decl.v
@@ -42,4 +42,17 @@ module top;
                 $display("5: ", ~a[j * 8 + k] + 11);
     end
 
+    initial begin : foo_6
+        integer i;
+        for (i = 0; i < 32; i = i + 1)
+            $display("6: ", ~a[i]);
+    end
+
+    initial begin : foo_7
+        integer j, k;
+        for (j = 0; j < 4; j++)
+            for (k = 0; k < 8; k++)
+                $display("7: ", ~a[j * 8 + k] + 11);
+    end
+
 endmodule