diff --git a/Language/SystemVerilog/AST.hs b/Language/SystemVerilog/AST.hs
index ae30a4d..4ac990c 100644
--- a/Language/SystemVerilog/AST.hs
+++ b/Language/SystemVerilog/AST.hs
@@ -228,6 +228,8 @@ data BinOp
   | Le
   | Gt
   | Ge
+  | ShiftAL
+  | ShiftAR
   deriving Eq
 
 instance Show BinOp where
@@ -250,6 +252,8 @@ instance Show BinOp where
     Le     -> "<="
     Gt     -> ">"
     Ge     -> ">="
+    ShiftAL -> "<<<"
+    ShiftAR -> ">>>"
 
 instance Show Expr where
   show x = case x of
diff --git a/Language/SystemVerilog/Parser/Parse.y b/Language/SystemVerilog/Parser/Parse.y
index 97bdb9b..7a8020b 100644
--- a/Language/SystemVerilog/Parser/Parse.y
+++ b/Language/SystemVerilog/Parser/Parse.y
@@ -148,7 +148,7 @@ string             { Token Lit_string    _ _ }
 %left  "&" "~&"
 %left  "==" "!=" "===" "!=="
 %left  "<" "<=" ">" ">="
-%left  "<<" ">>"
+%left  "<<" ">>" "<<<" ">>>"
 %left  "+" "-"
 %left  "*" "/" "%"
 %left  UPlus UMinus "!" "~" RedOps
@@ -420,6 +420,8 @@ Expr :: { Expr }
 | Expr "*"  Expr              { BinOp Mul $1 $3 }
 | Expr "/"  Expr              { BinOp Div $1 $3 }
 | Expr "%"  Expr              { BinOp Mod $1 $3 }
+| Expr "<<<" Expr             { BinOp ShiftAL $1 $3 }
+| Expr ">>>" Expr             { BinOp ShiftAR $1 $3 }
 | "!" Expr                    { UniOp Not $2 }
 | "~" Expr                    { UniOp BWNot $2 }
 | "+" Expr %prec UPlus        { UniOp UAdd $2 }