diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index 4bd3d4f..5e871cb 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -1173,6 +1173,9 @@ CycleDelay :: { Expr }
 EventControl :: { Sense }
   : "@" "(" Senses ")" { $3 }
   | "@" "(*)"          { SenseStar }
+  | "@" "(" "*" ")"    { SenseStar }
+  | "@" "(*" ")"       { SenseStar }
+  | "@" "(" "*)"       { SenseStar }
   | "@*"               { SenseStar }
   | "@" Identifier     { Sense $ LHSIdent $2 }
 Senses :: { Sense }
diff --git a/test/basic/sense_star.sv b/test/basic/sense_star.sv
new file mode 100644
index 0000000..091484a
--- /dev/null
+++ b/test/basic/sense_star.sv
@@ -0,0 +1,16 @@
+module top;
+`define TEST(sense) always sense $display(`"sense %b`", x);
+    reg x, y;
+    `TEST(@*)
+    `TEST(@x)
+    `TEST(@y)
+    `TEST(@ ( * ))
+    `TEST(@ ( *))
+    `TEST(@ (* ))
+    `TEST(@ (*))
+    `TEST(@( * ))
+    `TEST(@( *))
+    `TEST(@(* ))
+    `TEST(@(*))
+    initial x = 1;
+endmodule