diff --git a/CHANGELOG.md b/CHANGELOG.md
index 9f301ff..588f320 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -7,8 +7,8 @@
 
 ### New Features
 
-* `unique`, `unique0`, and `priority` case statements now are prefaced
-  with `parallel_case` and `full_case` attributes
+* `unique`, `unique0`, and `priority` case statements now produce corresponding
+  `parallel_case` and `full_case` statement attributes
 * Added support for attributes in unary, binary, and ternary expressions
 * Added support for shadowing interface names with local typenames
 * Added support for streaming concatenations within ternary expressions
diff --git a/src/Convert/Unique.hs b/src/Convert/Unique.hs
index 866f314..9069bc3 100644
--- a/src/Convert/Unique.hs
+++ b/src/Convert/Unique.hs
@@ -3,8 +3,9 @@
  -
  - Conversion for `unique`, `unique0`, and `priority` (verification checks)
  -
- - This conversion adds full_case and parallel_case synthesis attributes
- - for priority and unique modifiers on case statements.
+ - For `case`, these verification checks are replaced with equivalent
+ - `full_case` and `parallel_case` attributes. For `if`, they are simply
+ - dropped.
  -}
 
 module Convert.Unique (convert) where
diff --git a/test/core/case_violation_checks.sv b/test/core/case_violation_checks.sv
index 5d2824f..8d5ba40 100644
--- a/test/core/case_violation_checks.sv
+++ b/test/core/case_violation_checks.sv
@@ -1,19 +1,10 @@
-module top;
-    reg [1:0] select;
-    logic [3:0] data [2:0];
-    UniqueCase case0(.select, .data(data[0]));
-    Unique0Case case1(.select, .data(data[1]));
-    PriorityCase case2(.select, .data(data[2]));
-    initial begin end
-endmodule
-
 module UniqueCase(
     input logic [1:0] select,
     output logic [3:0] data
 );
     always_comb begin
         data = 4'b0;
-        unique case(select)
+        unique case (select)
             2'd0: data = 4'ha;
             2'd1: data = 4'h6;
             2'd2: data = 4'h3;
@@ -27,7 +18,7 @@ module Unique0Case(
 );
     always_comb begin
         data = 4'b0;
-        unique0 case(select)
+        unique0 case (select)
             2'd0: data = 4'ha;
             2'd1: data = 4'h6;
             2'd2: data = 4'h3;
@@ -41,7 +32,7 @@ module PriorityCase(
 );
     always_comb begin
         data = 4'b0;
-        priority case(select)
+        priority case (select)
             2'd0: data = 4'ha;
             2'd1: data = 4'h6;
             2'd2: data = 4'h3;
diff --git a/test/core/case_violation_checks.v b/test/core/case_violation_checks.v
index 67587c1..684faba 100644
--- a/test/core/case_violation_checks.v
+++ b/test/core/case_violation_checks.v
@@ -1,19 +1,10 @@
-module top;
-    reg [1:0] select;
-    wire [3:0] data [2:0];
-    UniqueCase case0(.select(select), .data(data[0]));
-    Unique0Case case1(.select(select), .data(data[1]));
-    PriorityCase case2(.select(select), .data(data[2]));
-    initial begin end
-endmodule
-
 module UniqueCase(
-    input [1:0] select,
+    input wire [1:0] select,
     output reg [3:0] data
 );
     always @* begin
         data = 4'b0;
-        case(select)
+        case (select)
             2'd0: data = 4'ha;
             2'd1: data = 4'h6;
             2'd2: data = 4'h3;
@@ -22,12 +13,12 @@ module UniqueCase(
 endmodule
 
 module Unique0Case(
-    input [1:0] select,
+    input wire [1:0] select,
     output reg [3:0] data
 );
     always @* begin
         data = 4'b0;
-        case(select)
+        case (select)
             2'd0: data = 4'ha;
             2'd1: data = 4'h6;
             2'd2: data = 4'h3;
@@ -36,12 +27,12 @@ module Unique0Case(
 endmodule
 
 module PriorityCase(
-    input [1:0] select,
+    input wire [1:0] select,
     output reg [3:0] data
 );
     always @* begin
         data = 4'b0;
-        case(select)
+        case (select)
             2'd0: data = 4'ha;
             2'd1: data = 4'h6;
             2'd2: data = 4'h3;
diff --git a/test/core/case_violation_checks_tb.v b/test/core/case_violation_checks_tb.v
new file mode 100644
index 0000000..ca1bb86
--- /dev/null
+++ b/test/core/case_violation_checks_tb.v
@@ -0,0 +1,7 @@
+module top;
+    reg [1:0] select;
+    wire [3:0] data [2:0];
+    UniqueCase case0(select, data[0]);
+    Unique0Case case1(select, data[1]);
+    PriorityCase case2(select, data[2]);
+endmodule