From c722e931fe12c8b3f1c55eabac1004e776f095d1 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Fri, 11 Oct 2019 22:56:16 -0400
Subject: [PATCH] allow time delay values

---
 src/Language/SystemVerilog/Parser/Parse.y | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index 6aae3ce..b9d726e 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -1030,13 +1030,10 @@ Sense :: { Sense }
 
 DelayValue :: { Expr }
   : Number { Number $1 }
+  | Time   { Time   $1 }
   | Identifier { Ident $1 }
   | Identifier "::" Identifier { PSIdent $1 $3 }
   | "(" Expr ":" Expr ":" Expr ")" { MinTypMax $2 $4 $6 }
--- TODO: Support these other DelayValues?
--- | real_number
--- | time_literal
--- | 1step
 
 CaseKW :: { CaseKW }
   : "case"  { CaseN }