diff --git a/src/Convert/Traverse.hs b/src/Convert/Traverse.hs
index 0b0cd1e..a74593b 100644
--- a/src/Convert/Traverse.hs
+++ b/src/Convert/Traverse.hs
@@ -251,7 +251,7 @@ traverseSinglyNestedStmtsM fullMapper = cs
         cs (Timing event stmt) = fullMapper stmt >>= return . Timing event
         cs (Return expr) = return $ Return expr
         cs (Subroutine ps f exprs) = return $ Subroutine ps f exprs
-        cs (Trigger x) = return $ Trigger x
+        cs (Trigger blocks x) = return $ Trigger blocks x
         cs (Assertion a) =
             traverseAssertionStmtsM fullMapper a >>= return . Assertion
         cs (Null) = return Null
@@ -703,7 +703,7 @@ traverseStmtExprsM exprMapper = flatStmtMapper
         return $ Subroutine ps f (Args l' p')
     flatStmtMapper (Return expr) =
         exprMapper expr >>= return . Return
-    flatStmtMapper (Trigger x) = return $ Trigger x
+    flatStmtMapper (Trigger blocks x) = return $ Trigger blocks x
     flatStmtMapper (Assertion a) = do
         a' <- traverseAssertionStmtsM stmtMapper a
         a'' <- traverseAssertionExprsM exprMapper a'
diff --git a/src/Language/SystemVerilog/AST/Stmt.hs b/src/Language/SystemVerilog/AST/Stmt.hs
index 364f55f..ee60b31 100644
--- a/src/Language/SystemVerilog/AST/Stmt.hs
+++ b/src/Language/SystemVerilog/AST/Stmt.hs
@@ -49,7 +49,7 @@ data Stmt
     | Timing  Timing Stmt
     | Return  Expr
     | Subroutine (Maybe Identifier) Identifier Args
-    | Trigger Identifier
+    | Trigger Bool Identifier
     | Assertion Assertion
     | Null
     deriving Eq
@@ -94,7 +94,7 @@ instance Show Stmt where
     show (If u a b c   ) = printf "%sif (%s) %s\nelse %s" (maybe "" showPad u) (show a) (show b) (show c)
     show (Return e   ) = printf "return %s;" (show e)
     show (Timing t s ) = printf "%s %s" (show t) (show s)
-    show (Trigger x  ) = printf "-> %s;" x
+    show (Trigger b x) = printf "->%s %s;" (if b then "" else ">") x
     show (Assertion a) = show a
     show (Null       ) = ";"
 
diff --git a/src/Language/SystemVerilog/AST/Type.hs b/src/Language/SystemVerilog/AST/Type.hs
index 047727b..8347dbd 100644
--- a/src/Language/SystemVerilog/AST/Type.hs
+++ b/src/Language/SystemVerilog/AST/Type.hs
@@ -148,6 +148,7 @@ data NonIntegerType
     | TReal
     | TRealtime
     | TString
+    | TEvent
     deriving (Eq, Ord)
 
 instance Show NetType where
@@ -179,6 +180,7 @@ instance Show NonIntegerType where
     show TReal      = "real"
     show TRealtime  = "realtime"
     show TString    = "string"
+    show TEvent     = "event"
 
 data Packing
     = Unpacked
diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index 4eaf7e7..4081da6 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -486,6 +486,7 @@ NonIntegerType :: { NonIntegerType }
   | "real"      { TReal      }
   | "realtime"  { TRealtime  }
   | "string"    { TString    }
+  | "event"     { TEvent     }
 
 EnumItems :: { [(Identifier, Maybe Expr)] }
   : VariablePortIdentifiers { $1 }
@@ -915,7 +916,8 @@ StmtNonBlock :: { Stmt }
   | "do"      Stmt "while" "(" Expr ")" ";"    { DoWhile $5 $2 }
   | "forever" Stmt                             { Forever $2 }
   | "foreach" "(" Identifier IdxVars ")" Stmt  { Foreach $3 $4 $6 }
-  | "->" Identifier ";"                        { Trigger $2 }
+  | "->"  Identifier ";"                       { Trigger True  $2 }
+  | "->>" Identifier ";"                       { Trigger False $2 }
   | AttributeInstance Stmt                     { StmtAttr $1 $2 }
   | ProceduralAssertionStatement               { Assertion $1 }
   | IncOrDecOperator LHS ";"                   { AsgnBlk (AsgnOp $1) $2 (Number "1") }
@@ -1000,6 +1002,7 @@ EventControl :: { Sense }
   : "@" "(" Senses ")" { $3 }
   | "@" "(*)"          { SenseStar }
   | "@*"               { SenseStar }
+  | "@" Identifier     { Sense $ LHSIdent $2 }
 Senses :: { Sense }
   : Sense             { $1 }
   | Senses "or" Sense { SenseOr $1 $3 }