diff --git a/src/Convert/Interface.hs b/src/Convert/Interface.hs
index 6a3fc7d..68d1afb 100644
--- a/src/Convert/Interface.hs
+++ b/src/Convert/Interface.hs
@@ -260,8 +260,8 @@ convertDescription parts (Part attrs extern Module lifetime name ports items) =
                 collectDecl _ = return ()
 
         extractModportInfo :: Type -> Maybe Identifier
-        extractModportInfo (InterfaceT "" Nothing []) = Just ""
-        extractModportInfo (InterfaceT interfaceName (Just modportName) []) =
+        extractModportInfo (InterfaceT "" "" []) = Just ""
+        extractModportInfo (InterfaceT interfaceName modportName []) =
             if isInterface interfaceName
                 then Just modportName
                 else Nothing
diff --git a/src/Convert/Traverse.hs b/src/Convert/Traverse.hs
index 7c06424..757a4e0 100644
--- a/src/Convert/Traverse.hs
+++ b/src/Convert/Traverse.hs
@@ -798,7 +798,7 @@ traverseSinglyNestedTypesM mapper = tm
         tm (IntegerAtom   kw sg   ) = return $ IntegerAtom   kw sg
         tm (NonInteger    kw      ) = return $ NonInteger    kw
         tm (TypeOf        expr    ) = return $ TypeOf        expr
-        tm (InterfaceT x my r) = return $ InterfaceT x my r
+        tm (InterfaceT x y r) = return $ InterfaceT x y r
         tm (Enum t vals r) = do
             t' <- mapper t
             return $ Enum t' vals r
diff --git a/src/Language/SystemVerilog/AST/Type.hs b/src/Language/SystemVerilog/AST/Type.hs
index 1aafa5c..390c3a9 100644
--- a/src/Language/SystemVerilog/AST/Type.hs
+++ b/src/Language/SystemVerilog/AST/Type.hs
@@ -49,7 +49,7 @@ data Type
     | Enum     Type         [Item]             [Range]
     | Struct   Packing      [Field]            [Range]
     | Union    Packing      [Field]            [Range]
-    | InterfaceT Identifier (Maybe Identifier) [Range]
+    | InterfaceT Identifier Identifier         [Range]
     | TypeOf Expr
     | UnpackedType Type [Range] -- used internally
     deriving (Eq, Ord)
@@ -63,8 +63,8 @@ instance Show Type where
     show (IntegerVector kw sg rs) = printf "%s%s%s" (show kw) (showPadBefore sg) (showRanges rs)
     show (IntegerAtom   kw sg   ) = printf "%s%s"   (show kw) (showPadBefore sg)
     show (NonInteger    kw      ) = printf "%s"     (show kw)
-    show (InterfaceT x my r) = x ++ yStr ++ (showRanges r)
-        where yStr = maybe "" ("."++) my
+    show (InterfaceT x y r) = x ++ yStr ++ (showRanges r)
+        where yStr = if null y then "" else '.' : y
     show (Enum t vals r) = printf "enum %s{%s}%s" tStr (commas $ map showVal vals) (showRanges r)
         where
             tStr = showPad t
@@ -104,7 +104,7 @@ typeRanges typ =
         Enum            t v rs -> (Enum            t v, rs)
         Struct          p l rs -> (Struct          p l, rs)
         Union           p l rs -> (Union           p l, rs)
-        InterfaceT     x my rs -> (InterfaceT     x my, rs)
+        InterfaceT      x y rs -> (InterfaceT      x y, rs)
         Alias            xx rs -> (Alias            xx, rs)
         PSAlias    ps    xx rs -> (PSAlias    ps    xx, rs)
         CSAlias    ps pm xx rs -> (CSAlias    ps pm xx, rs)
diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index a95a509..a55d3b5 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -661,7 +661,7 @@ PortDeclTokens(delim) :: { [DeclToken] }
   | GenericInterfaceDecl                  delim  { $1 }
   | AttributeInstance      PortDeclTokens(delim) {% posInject \p -> DTAttr p $1 : $2 }
 GenericInterfaceDecl :: { [DeclToken] }
-  : "interface" Identifier {% posInject \p -> [DTType p (\Unspecified -> InterfaceT "" Nothing), DTIdent p $2] }
+  : "interface" Identifier {% posInject \p -> [DTType p (\Unspecified -> InterfaceT "" ""), DTIdent p $2] }
 
 VariablePortIdentifiers :: { [(Identifier, Expr)] }
   : VariablePortIdentifier                             { [$1] }
diff --git a/src/Language/SystemVerilog/Parser/ParseDecl.hs b/src/Language/SystemVerilog/Parser/ParseDecl.hs
index ca46637..0052df5 100644
--- a/src/Language/SystemVerilog/Parser/ParseDecl.hs
+++ b/src/Language/SystemVerilog/Parser/ParseDecl.hs
@@ -434,7 +434,7 @@ takeLifetime (DTLifetime _ l : rest) = (Just  l, rest)
 takeLifetime                   rest  = (Nothing, rest)
 
 takeType :: [DeclToken] -> ([Range] -> Type, [DeclToken])
-takeType (DTIdent _ a  : DTDot _ b      : rest) = (InterfaceT a (Just b), rest)
+takeType (DTIdent _ a  : DTDot _ b      : rest) = (InterfaceT a  b      , rest)
 takeType (DTType  _ tf : DTSigning _ sg : rest) = (tf       sg          , rest)
 takeType (DTType  _ tf                  : rest) = (tf       Unspecified , rest)
 takeType (DTSigning _ sg                : rest) = (Implicit sg          , rest)