diff --git a/src/Convert/UnpackedArray.hs b/src/Convert/UnpackedArray.hs
index 80cc005..2165ca4 100644
--- a/src/Convert/UnpackedArray.hs
+++ b/src/Convert/UnpackedArray.hs
@@ -85,7 +85,10 @@ traverseStmtM stmt =
     traverseStmtAsgnsM traverseAsgnM
 
 traverseExprM :: Expr -> ST Expr
-traverseExprM = return
+traverseExprM (Range (Ident x) mode i) = do
+    flatUsageM x
+    return $ Range (Ident x) mode i
+traverseExprM other = return other
 
 traverseLHSM :: LHS -> ST LHS
 traverseLHSM (LHSIdent x) = do
diff --git a/test/basic/multipack_port.sv b/test/basic/multipack_port.sv
index 8453f61..f19f73c 100644
--- a/test/basic/multipack_port.sv
+++ b/test/basic/multipack_port.sv
@@ -1,7 +1,8 @@
-module foo(clock, data);
+module Producer(clock, data);
+    parameter INIT = 0;
     input logic clock;
     output logic [10:0] data [5];
-    initial data[0][0] = 0;
+    initial data[0][0] = INIT;
     always @(clock) begin
         integer i, j;
         for (i = 4; i >= 0; i--) begin
@@ -16,17 +17,24 @@ module foo(clock, data);
 endmodule
 
 module top;
-  logic [10:0] data [5];
     reg clock;
-    foo f(clock, data);
-
     initial begin
         clock = 1;
         repeat (100)
             #1 clock = ~clock;
     end
 
-    initial begin : foo
-        $monitor("%d %b%b%b%b%b", $time, data[0], data[1], data[2], data[3], data[4]);
-    end
+    logic [10:0] foo [5];
+    Producer #(.INIT(0)) p1(clock, foo);
+
+    logic [10:0] bar [10];
+    Producer #(.INIT(0)) p2(clock, bar[0:4]);
+    Producer #(.INIT(1)) p3(clock, bar[5:9]);
+
+    initial
+        $monitor("%d %b%b%b%b%b %b%b%b%b%b%b%b%b%b%b", $time,
+            foo[0], foo[1], foo[2], foo[3], foo[4],
+            bar[0], bar[1], bar[2], bar[3], bar[4],
+            bar[5], bar[6], bar[7], bar[8], bar[9]
+        );
 endmodule
diff --git a/test/basic/multipack_port.v b/test/basic/multipack_port.v
index e844879..a8f6296 100644
--- a/test/basic/multipack_port.v
+++ b/test/basic/multipack_port.v
@@ -1,7 +1,8 @@
-module foo(clock, data);
+module Producer(clock, data);
+    parameter INIT = 0;
     input clock;
     output reg [54:0] data;
-    initial data[11*4] = 0;
+    initial data[11*4] = INIT;
     always @(clock) begin : block_name
         integer i, j;
         for (i = 4; i >= 0; i--) begin
@@ -16,17 +17,20 @@ module foo(clock, data);
 endmodule
 
 module top;
-    wire [54:0] data;
     reg clock;
-    foo f(clock, data);
-
     initial begin
         clock = 1;
         repeat (100)
             #1 clock = ~clock;
     end
 
-    initial begin : foo
-        $monitor("%d %b", $time, data);
-    end
+    wire [54:0] foo;
+    Producer #(.INIT(0)) p1(clock, foo);
+
+    wire [109:0] bar;
+    Producer #(.INIT(0)) p2(clock, bar[54:0]);
+    Producer #(.INIT(1)) p3(clock, bar[109:55]);
+
+    initial
+        $monitor("%d %b %b", $time, foo, bar);
 endmodule