diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index c731960..da9f720 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -942,7 +942,8 @@ PortBinding :: { PortBinding }
   | ".*"                             { ("*", Nothing) }
 
 ParamBindings :: { [ParamBinding] }
-  : "#" "(" ParamBindingsInside ")" { $3 }
+  : "#" "("                     ")" { [] }
+  | "#" "(" ParamBindingsInside ")" { $3 }
 ParamBindingsInside :: { [ParamBinding] }
   : ParamBinding                         { [$1] }
   | ParamBinding "," ParamBindingsInside { $1 : $3}