From ba7fbd55065d409d5abd457b775fca021effd480 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Thu, 3 Oct 2019 23:29:49 -0400 Subject: [PATCH] allow escaped newline in macro arguments --- src/Language/SystemVerilog/Parser/Lex.x | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/Language/SystemVerilog/Parser/Lex.x b/src/Language/SystemVerilog/Parser/Lex.x index 20a4e89..5fd260f 100644 --- a/src/Language/SystemVerilog/Parser/Lex.x +++ b/src/Language/SystemVerilog/Parser/Lex.x @@ -755,7 +755,11 @@ takeMacroArguments = do case (stack, ch) of ( s,'\\') -> do ch2 <- takeChar - loop (curr ++ [ch, ch2]) s + if ch2 == '\n' + then do + dropWhitespace + loop curr s + else loop (curr ++ [ch, ch2]) s ([ ], ',') -> return (curr, False) ([ ], ')') -> return (curr, True)