From b660cfbd4ec9bf24ec049fff8c323b35b886dda0 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Thu, 10 Oct 2019 22:10:59 -0400
Subject: [PATCH] allow tabs in preprocessor directives

---
 src/Language/SystemVerilog/Parser/Lex.x | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/Language/SystemVerilog/Parser/Lex.x b/src/Language/SystemVerilog/Parser/Lex.x
index 29471ac..c963c0c 100644
--- a/src/Language/SystemVerilog/Parser/Lex.x
+++ b/src/Language/SystemVerilog/Parser/Lex.x
@@ -682,12 +682,15 @@ takeChar = do
 dropSpaces :: Alex ()
 dropSpaces = do
     (pos, _, _, str) <- alexGetInput
-    case str of
-        ' ' : rest -> do
-            alexSetInput (alexMove pos ' ', ' ', [], rest)
+    if null str then
+        return ()
+    else do
+        let ch : rest = str
+        if ch == '\t' || ch == ' ' then do
+            alexSetInput (alexMove pos ch, ch, [], tail str)
             dropSpaces
-        [] -> return ()
-        _ -> return ()
+        else
+            return ()
 
 isWhitespaceChar :: Char -> Bool
 isWhitespaceChar ch = elem ch [' ', '\t', '\n']