From b5b9fdb37eba97892e67097f9729949bf6d890c5 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Fri, 8 Mar 2019 16:55:03 -0500 Subject: [PATCH] support for null call arguments --- src/Convert/Traverse.hs | 7 +++++-- src/Language/SystemVerilog/AST.hs | 8 ++++---- src/Language/SystemVerilog/Parser/Parse.y | 14 ++++++++------ 3 files changed, 17 insertions(+), 12 deletions(-) diff --git a/src/Convert/Traverse.hs b/src/Convert/Traverse.hs index 4cc4b61..89b0acf 100644 --- a/src/Convert/Traverse.hs +++ b/src/Convert/Traverse.hs @@ -180,6 +180,9 @@ traverseNestedExprsM :: Monad m => MapperM m Expr -> MapperM m Expr traverseNestedExprsM mapper = exprMapper where exprMapper e = mapper e >>= em + maybeExprMapper Nothing = return Nothing + maybeExprMapper (Just e) = + exprMapper e >>= return . Just em (String s) = return $ String s em (Number s) = return $ Number s em (ConstBool b) = return $ ConstBool b @@ -200,7 +203,7 @@ traverseNestedExprsM mapper = exprMapper em (Concat l) = mapM exprMapper l >>= return . Concat em (Call f l) = - mapM exprMapper l >>= return . Call f + mapM maybeExprMapper l >>= return . Call f em (UniOp o e) = exprMapper e >>= return . UniOp o em (BinOp o e1 e2) = do @@ -277,7 +280,7 @@ traverseExprsM mapper = moduleItemMapper exprMapper cc >>= \cc' -> return $ If cc' s1 s2 flatStmtMapper (Timing event stmt) = return $ Timing event stmt flatStmtMapper (Subroutine f exprs) = - mapM exprMapper exprs >>= return . Subroutine f + mapM maybeExprMapper exprs >>= return . Subroutine f flatStmtMapper (Return expr) = exprMapper expr >>= return . Return flatStmtMapper (Null) = return Null diff --git a/src/Language/SystemVerilog/AST.hs b/src/Language/SystemVerilog/AST.hs index b5c39d4..4392424 100644 --- a/src/Language/SystemVerilog/AST.hs +++ b/src/Language/SystemVerilog/AST.hs @@ -269,7 +269,7 @@ data Expr | Bit Expr Expr | Repeat Expr [Expr] | Concat [Expr] - | Call Identifier [Expr] + | Call Identifier [Maybe Expr] | UniOp UniOp Expr | BinOp BinOp Expr Expr | Mux Expr Expr Expr @@ -369,7 +369,7 @@ instance Show Expr where Range a (b, c) -> printf "%s[%s:%s]" (show a) (show b) (show c) Repeat a b -> printf "{%s {%s}}" (show a) (commas $ map show b) Concat a -> printf "{%s}" (commas $ map show a) - Call a b -> printf "%s(%s)" a (commas $ map show b) + Call a b -> printf "%s(%s)" a (commas $ map (maybe "" show) b) UniOp a b -> printf "(%s %s)" (show a) (show b) BinOp a b c -> printf "(%s %s %s)" (show b) (show a) (show c) Mux a b c -> printf "(%s ? %s : %s)" (show a) (show b) (show c) @@ -431,7 +431,7 @@ data Stmt | If Expr Stmt Stmt | Timing Timing Stmt | Return Expr - | Subroutine Identifier [Expr] + | Subroutine Identifier [Maybe Expr] | Null deriving Eq @@ -462,7 +462,7 @@ instance Show Stmt where show (If a b Null) = printf "if (%s) %s" (show a) (show b) show (If a b c ) = printf "if (%s) %s\nelse %s" (show a) (show b) (show c) show (Return e ) = printf "return %s;" (show e) - show (Subroutine x a) = printf "%s(%s);" x (commas $ map show a) + show (Subroutine x a) = printf "%s(%s);" x (commas $ map (maybe "" show) a) show (Timing t s ) = printf "%s%s" (show t) rest where rest = case s of diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y index 2f9c20b..2c5066e 100644 --- a/src/Language/SystemVerilog/Parser/Parse.y +++ b/src/Language/SystemVerilog/Parser/Parse.y @@ -479,12 +479,14 @@ Number :: { String } String :: { String } : string { tail $ init $ tokenString $1 } -CallArgs :: { [Expr] } - : {- empty -} { [] } - | CallArgsNonEmpty { $1 } -CallArgsNonEmpty :: { [Expr] } - : Expr { [$1] } - | CallArgsNonEmpty "," Expr { $1 ++ [$3] } +CallArgs :: { [Maybe Expr] } + : {- empty -} { [] } + | Expr { [Just $1] } + | CallArgsFollow { (Nothing) : $1 } + | Expr CallArgsFollow { (Just $1) : $2 } +CallArgsFollow :: { [Maybe Expr] } + : "," opt(Expr) { [$2] } + | "," opt(Expr) CallArgsFollow { $2 : $3 } Exprs :: { [Expr] } : Expr { [$1] }