From b46009af531a0a709c068fd61874ab8e17d1b477 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Fri, 8 Feb 2019 00:19:39 -0500 Subject: [PATCH] Refactor project setup for our purposes --- Language/SystemVerilog.hs | 9 +++ Language/{Verilog => SystemVerilog}/AST.hs | 2 +- Language/{Verilog => SystemVerilog}/Parser.hs | 12 ++-- .../{Verilog => SystemVerilog}/Parser/Lex.x | 4 +- .../{Verilog => SystemVerilog}/Parser/Parse.y | 6 +- .../Parser/Preprocess.hs | 2 +- .../Parser/Tokens.hs | 2 +- .../{Verilog => SystemVerilog}/Simulator.hs | 4 +- Language/Verilog.hs | 9 --- sv2v.cabal | 61 +++++++++++++++++++ sv2v.hs | 18 ++++++ verilog.cabal | 47 -------------- 12 files changed, 104 insertions(+), 72 deletions(-) create mode 100644 Language/SystemVerilog.hs rename Language/{Verilog => SystemVerilog}/AST.hs (99%) rename Language/{Verilog => SystemVerilog}/Parser.hs (63%) rename Language/{Verilog => SystemVerilog}/Parser/Lex.x (98%) rename Language/{Verilog => SystemVerilog}/Parser/Parse.y (98%) rename Language/{Verilog => SystemVerilog}/Parser/Preprocess.hs (98%) rename Language/{Verilog => SystemVerilog}/Parser/Tokens.hs (99%) rename Language/{Verilog => SystemVerilog}/Simulator.hs (98%) delete mode 100644 Language/Verilog.hs create mode 100644 sv2v.cabal create mode 100644 sv2v.hs delete mode 100644 verilog.cabal diff --git a/Language/SystemVerilog.hs b/Language/SystemVerilog.hs new file mode 100644 index 0000000..90d6a2f --- /dev/null +++ b/Language/SystemVerilog.hs @@ -0,0 +1,9 @@ +-- | A parser for SystemVerilog. +module Language.SystemVerilog + ( module Language.SystemVerilog.AST + , module Language.SystemVerilog.Parser + ) where + +import Language.SystemVerilog.AST +import Language.SystemVerilog.Parser + diff --git a/Language/Verilog/AST.hs b/Language/SystemVerilog/AST.hs similarity index 99% rename from Language/Verilog/AST.hs rename to Language/SystemVerilog/AST.hs index 3b2db16..d8f9d91 100644 --- a/Language/Verilog/AST.hs +++ b/Language/SystemVerilog/AST.hs @@ -1,4 +1,4 @@ -module Language.Verilog.AST +module Language.SystemVerilog.AST ( Identifier , Module (..) , ModuleItem (..) diff --git a/Language/Verilog/Parser.hs b/Language/SystemVerilog/Parser.hs similarity index 63% rename from Language/Verilog/Parser.hs rename to Language/SystemVerilog/Parser.hs index 3e6aa98..d4f2719 100644 --- a/Language/Verilog/Parser.hs +++ b/Language/SystemVerilog/Parser.hs @@ -1,13 +1,13 @@ -module Language.Verilog.Parser +module Language.SystemVerilog.Parser ( parseFile , preprocess ) where -import Language.Verilog.AST -import Language.Verilog.Parser.Lex -import Language.Verilog.Parser.Parse -import Language.Verilog.Parser.Preprocess -import Language.Verilog.Parser.Tokens +import Language.SystemVerilog.AST +import Language.SystemVerilog.Parser.Lex +import Language.SystemVerilog.Parser.Parse +import Language.SystemVerilog.Parser.Preprocess +import Language.SystemVerilog.Parser.Tokens -- | Parses a file given a table of predefined macros, the file name, and the file contents. parseFile :: [(String, String)] -> FilePath -> String -> [Module] diff --git a/Language/Verilog/Parser/Lex.x b/Language/SystemVerilog/Parser/Lex.x similarity index 98% rename from Language/Verilog/Parser/Lex.x rename to Language/SystemVerilog/Parser/Lex.x index 177f6af..6f25b86 100644 --- a/Language/Verilog/Parser/Lex.x +++ b/Language/SystemVerilog/Parser/Lex.x @@ -1,10 +1,10 @@ { {-# OPTIONS_GHC -w #-} -module Language.Verilog.Parser.Lex +module Language.SystemVerilog.Parser.Lex ( alexScanTokens ) where -import Language.Verilog.Parser.Tokens +import Language.SystemVerilog.Parser.Tokens } diff --git a/Language/Verilog/Parser/Parse.y b/Language/SystemVerilog/Parser/Parse.y similarity index 98% rename from Language/Verilog/Parser/Parse.y rename to Language/SystemVerilog/Parser/Parse.y index 501c139..a1676d3 100644 --- a/Language/Verilog/Parser/Parse.y +++ b/Language/SystemVerilog/Parser/Parse.y @@ -1,12 +1,12 @@ { -module Language.Verilog.Parser.Parse (modules) where +module Language.SystemVerilog.Parser.Parse (modules) where import Data.Bits import Data.List import Data.BitVec -import Language.Verilog.AST -import Language.Verilog.Parser.Tokens +import Language.SystemVerilog.AST +import Language.SystemVerilog.Parser.Tokens } %name modules diff --git a/Language/Verilog/Parser/Preprocess.hs b/Language/SystemVerilog/Parser/Preprocess.hs similarity index 98% rename from Language/Verilog/Parser/Preprocess.hs rename to Language/SystemVerilog/Parser/Preprocess.hs index 782e792..607d3e7 100644 --- a/Language/Verilog/Parser/Preprocess.hs +++ b/Language/SystemVerilog/Parser/Preprocess.hs @@ -1,4 +1,4 @@ -module Language.Verilog.Parser.Preprocess +module Language.SystemVerilog.Parser.Preprocess ( uncomment , preprocess ) where diff --git a/Language/Verilog/Parser/Tokens.hs b/Language/SystemVerilog/Parser/Tokens.hs similarity index 99% rename from Language/Verilog/Parser/Tokens.hs rename to Language/SystemVerilog/Parser/Tokens.hs index ee60dda..317daed 100644 --- a/Language/Verilog/Parser/Tokens.hs +++ b/Language/SystemVerilog/Parser/Tokens.hs @@ -1,4 +1,4 @@ -module Language.Verilog.Parser.Tokens +module Language.SystemVerilog.Parser.Tokens ( Token (..) , TokenName (..) , Position (..) diff --git a/Language/Verilog/Simulator.hs b/Language/SystemVerilog/Simulator.hs similarity index 98% rename from Language/Verilog/Simulator.hs rename to Language/SystemVerilog/Simulator.hs index da60e85..b03e2a7 100644 --- a/Language/Verilog/Simulator.hs +++ b/Language/SystemVerilog/Simulator.hs @@ -1,4 +1,4 @@ -module Language.Verilog.Simulator +module Language.SystemVerilog.Simulator ( Simulator , SimCommand (..) , SimResponse (..) @@ -16,7 +16,7 @@ import Data.VCD hiding (Var, step) import qualified Data.VCD as VCD import Data.BitVec -import Language.Verilog.Netlist +import Language.SystemVerilog.Netlist --check msg = putStrLn msg >> hFlush stdout diff --git a/Language/Verilog.hs b/Language/Verilog.hs deleted file mode 100644 index c2067d5..0000000 --- a/Language/Verilog.hs +++ /dev/null @@ -1,9 +0,0 @@ --- | A parser for Verilog. -module Language.Verilog - ( module Language.Verilog.AST - , module Language.Verilog.Parser - ) where - -import Language.Verilog.AST -import Language.Verilog.Parser - diff --git a/sv2v.cabal b/sv2v.cabal new file mode 100644 index 0000000..a3ca195 --- /dev/null +++ b/sv2v.cabal @@ -0,0 +1,61 @@ +name: sv2v +version: 0.0.1 + +category: Language, Hardware, Embedded + +synopsis: SystemVerilog to Verilog conversion + +description: + A tool for coverting SystemVerilog to Verilog. Also exposes a limited + SystemVerilog parser and AST. Forked from the Verilog parser found at + https://github.com/tomahawkins/verilog + +author: Zachary Snow , Tom Hawkins +maintainer: Zachary Snow + +license: BSD3 +license-file: LICENSE + +homepage: https://github.com/zachjs/sv2v + +build-type: Simple +cabal-version: >= 1.10 + +library + default-language: Haskell2010 + build-tools: + alex >= 3 && < 4, + happy >= 1 && < 2 + build-depends: + base >= 4.8.2.0 && < 5.0, + array >= 0.5.1.0 && < 0.6 + + exposed-modules: + Data.BitVec + Language.SystemVerilog + Language.SystemVerilog.AST + Language.SystemVerilog.Parser + Language.SystemVerilog.Parser.Lex + Language.SystemVerilog.Parser.Parse + Language.SystemVerilog.Parser.Preprocess + Language.SystemVerilog.Parser.Tokens + + ghc-options: -W + +executable sv2v + default-language: Haskell2010 + main-is: sv2v.hs + Build-Depends: + base + ghc-options: + -O3 + -threaded + -rtsopts + -with-rtsopts=-N + -funbox-strict-fields + -Wall + +source-repository head + type: git + location: git://github.com/zachjs/sv2v.git + diff --git a/sv2v.hs b/sv2v.hs new file mode 100644 index 0000000..86ac6f5 --- /dev/null +++ b/sv2v.hs @@ -0,0 +1,18 @@ +{- sv2v + Author: Zachary Snow + + conversion entry point +-} + +import System.IO +import System.Exit + +main :: IO () +main = do + let res = Left "unimplemented" + case res of + Left err -> do + hPrint stderr err + exitFailure + Right _ -> do + exitSuccess diff --git a/verilog.cabal b/verilog.cabal deleted file mode 100644 index 9185677..0000000 --- a/verilog.cabal +++ /dev/null @@ -1,47 +0,0 @@ -name: verilog -version: 0.0.12 - -category: Language, Hardware, Embedded - -synopsis: Verilog preprocessor, parser, and AST. - -description: - A parser and supporting a small subset of Verilog. - Intended for machine generated, synthesizable code. - -author: Tom Hawkins -maintainer: Tom Hawkins - -license: BSD3 -license-file: LICENSE - -homepage: http://github.com/tomahawkins/verilog - -build-type: Simple -cabal-version: >= 1.10 - -library - default-language: Haskell2010 - build-tools: - alex >= 3 && < 4, - happy >= 1 && < 2 - build-depends: - base >= 4.8.2.0 && < 5.0, - array >= 0.5.1.0 && < 0.6 - - exposed-modules: - Data.BitVec - Language.Verilog - Language.Verilog.AST - Language.Verilog.Parser - Language.Verilog.Parser.Lex - Language.Verilog.Parser.Parse - Language.Verilog.Parser.Preprocess - Language.Verilog.Parser.Tokens - - ghc-options: -W - -source-repository head - type: git - location: git://github.com/tomahawkins/verilog.git -