diff --git a/src/Convert/UnpackedArray.hs b/src/Convert/UnpackedArray.hs index 1a397b1..80cc005 100644 --- a/src/Convert/UnpackedArray.hs +++ b/src/Convert/UnpackedArray.hs @@ -2,8 +2,8 @@ - Author: Zachary Snow - - Conversion for any unpacked array which must be packed because it is: A) a - - port; B) is bound to a port; or C) is assigned a value in a single - - assignment. + - port; B) is bound to a port; C) is assigned a value in a single assignment; + - or D) is assigned to an unpacked array which itself mus be packed. - - The scoped nature of declarations makes this challenging. While scoping is - obeyed in general, any of a set of *equivalent* declarations within a module @@ -64,6 +64,7 @@ traverseModuleItemM item = traverseModuleItemM' item >>= traverseLHSsM traverseLHSM >>= traverseExprsM traverseExprM + >>= traverseAsgnsM traverseAsgnM traverseModuleItemM' :: ModuleItem -> ST ModuleItem traverseModuleItemM' (Instance a b c d bindings) = do @@ -80,7 +81,8 @@ traverseModuleItemM' other = return other traverseStmtM :: Stmt -> ST Stmt traverseStmtM stmt = traverseStmtLHSsM traverseLHSM stmt >>= - traverseStmtExprsM traverseExprM + traverseStmtExprsM traverseExprM >>= + traverseStmtAsgnsM traverseAsgnM traverseExprM :: Expr -> ST Expr traverseExprM = return @@ -91,6 +93,13 @@ traverseLHSM (LHSIdent x) = do return $ LHSIdent x traverseLHSM other = return other +traverseAsgnM :: (LHS, Expr) -> ST (LHS, Expr) +traverseAsgnM (LHSIdent x, Ident y) = do + flatUsageM x + flatUsageM y + return (LHSIdent x, Ident y) +traverseAsgnM other = return other + flatUsageM :: Identifier -> ST () flatUsageM x = do declMap <- get diff --git a/test/basic/array.sv b/test/basic/array.sv new file mode 100644 index 0000000..fd8ebe1 --- /dev/null +++ b/test/basic/array.sv @@ -0,0 +1,5 @@ +module top; + logic [1:0] a [3]; + logic [1:0] b [3]; + always_comb a = b; +endmodule diff --git a/test/basic/array.v b/test/basic/array.v new file mode 100644 index 0000000..0dd1d29 --- /dev/null +++ b/test/basic/array.v @@ -0,0 +1,5 @@ +module top; + reg [5:0] a; + wire [5:0] b; + always @(*) a = b; +endmodule