diff --git a/src/Convert/ForDecl.hs b/src/Convert/ForDecl.hs
index 1589ddb..598e901 100644
--- a/src/Convert/ForDecl.hs
+++ b/src/Convert/ForDecl.hs
@@ -24,10 +24,10 @@ convert =
     )
 
 convertGenItem :: GenItem -> GenItem
-convertGenItem (GenFor (True, x, e) a b c d) =
-    GenBlock Nothing
+convertGenItem (GenFor (True, x, e) a b mx c) =
+    GenBlock (fmap (++ "_for_decl") mx)
     [ GenModuleItem $ Genvar x
-    , GenFor (False, x, e) a b c d
+    , GenFor (False, x, e) a b mx c
     ]
 convertGenItem other = other
 
diff --git a/test/basic/for_decl.sv b/test/basic/for_decl.sv
index 55a54dd..f2cf082 100644
--- a/test/basic/for_decl.sv
+++ b/test/basic/for_decl.sv
@@ -5,6 +5,11 @@ module top;
         assign a[n] = n & 1;
     end
 
+    wire [0:31] b;
+    for (genvar n = 0; n < 32; n++) begin : gen_filter_other
+        assign b[n] = ~a[n];
+    end
+
     initial
         for (integer i = 0; i < 32; i++)
             $display("1: ", a[i]);
@@ -49,4 +54,8 @@ module top;
         end
     end
 
+    initial
+        for (integer i = 0; i < 32; i++)
+            $display("8: ", a[i], b[i]);
+
 endmodule
diff --git a/test/basic/for_decl.v b/test/basic/for_decl.v
index c67df2b..04ef314 100644
--- a/test/basic/for_decl.v
+++ b/test/basic/for_decl.v
@@ -8,6 +8,14 @@ module top;
         end
     endgenerate
 
+    wire [0:31] b;
+    generate
+        genvar other_n;
+        for (other_n = 0; other_n < 32; other_n = other_n + 1) begin : gen_filter_other
+            assign b[other_n] = ~a[other_n];
+        end
+    endgenerate
+
     integer i;
     initial begin : foo_1
         for (i = 0; i < 32; i = i + 1)
@@ -55,4 +63,10 @@ module top;
                 $display("7: ", ~a[j * 8 + k] + 11);
     end
 
+    initial begin : foo_8
+        integer i;
+        for (i = 0; i < 32; i = i + 1)
+            $display("8: ", a[i], b[i]);
+    end
+
 endmodule
diff --git a/test/lib/functions.sh b/test/lib/functions.sh
index 966fc97..48c05e3 100644
--- a/test/lib/functions.sh
+++ b/test/lib/functions.sh
@@ -20,6 +20,7 @@ simulate() {
     iv_output=`iverilog \
         -Wall \
         -Wno-select-range \
+        -Wno-anachronisms \
         -o "$sim_prog" \
         -g2005 \
         -DTEST_VCD="\"$sim_vcd\"" \