From a7874e1b2fa2f1e265f8152461aa0a2e8e47d9f0 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Tue, 24 Nov 2020 18:09:07 -0700
Subject: [PATCH] test suite iverilog 11.0 compatibility

---
 test/basic/flatten.sv         | 18 +++++++++---------
 test/basic/flatten_tb.v       |  2 +-
 test/basic/flatten_three_tb.v |  2 +-
 test/basic/unsigned.sv        |  2 +-
 test/basic/unsigned.v         |  2 +-
 test/lex/macro_iv.sv          |  2 +-
 6 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/test/basic/flatten.sv b/test/basic/flatten.sv
index 8c9e5a6..5c2463b 100644
--- a/test/basic/flatten.sv
+++ b/test/basic/flatten.sv
@@ -6,15 +6,15 @@ module name(clock, in, out); \
     initial out[1+a] = 0; \
     initial out[2+a] = 0; \
     always @(posedge clock) begin \
-        $display($time, `" name @+ ", out[0+a][1+b+:1]); \
-        $display($time, `" name @+ ", out[1+a][1+b+:1]); \
-        $display($time, `" name @+ ", out[2+a][1+b+:1]); \
-        $display($time, `" name @+ ", out[0+a][1+b+:2]); \
-        $display($time, `" name @+ ", out[1+a][1+b+:2]); \
-        $display($time, `" name @+ ", out[2+a][1+b+:2]); \
-        $display($time, `" name @: ", out[0+a][1+b:1+b]); \
-        $display($time, `" name @: ", out[1+a][1+b:1+b]); \
-        $display($time, `" name @: ", out[2+a][1+b:1+b]); \
+        $display($time, `" name @+ `", out[0+a][1+b+:1]); \
+        $display($time, `" name @+ `", out[1+a][1+b+:1]); \
+        $display($time, `" name @+ `", out[2+a][1+b+:1]); \
+        $display($time, `" name @+ `", out[0+a][1+b+:2]); \
+        $display($time, `" name @+ `", out[1+a][1+b+:2]); \
+        $display($time, `" name @+ `", out[2+a][1+b+:2]); \
+        $display($time, `" name @: `", out[0+a][1+b:1+b]); \
+        $display($time, `" name @: `", out[1+a][1+b:1+b]); \
+        $display($time, `" name @: `", out[2+a][1+b:1+b]); \
  \
         out[2+a][4+b] = out[2+a][3+b]; \
         out[2+a][3+b] = out[2+a][2+b]; \
diff --git a/test/basic/flatten_tb.v b/test/basic/flatten_tb.v
index c38f6f2..31593f9 100644
--- a/test/basic/flatten_tb.v
+++ b/test/basic/flatten_tb.v
@@ -8,7 +8,7 @@
     initial begin \
         for (tag``i = 0; tag``i < 20; tag``i++) begin \
             #2; \
-            $display(`"tag", $time, ": %h %15b %15b %15b %15b", in, \
+            $display(`"tag`", $time, ": %h %15b %15b %15b %15b", in, \
                 tag``one_out, tag``two_out, tag``thr_out, tag``fou_out); \
         end \
     end
diff --git a/test/basic/flatten_three_tb.v b/test/basic/flatten_three_tb.v
index c642512..5d85070 100644
--- a/test/basic/flatten_three_tb.v
+++ b/test/basic/flatten_three_tb.v
@@ -8,7 +8,7 @@
     initial begin \
         for (tag``i = 0; tag``i < 40; tag``i++) begin \
             #2; \
-            $display(`"tag", $time, ": %h %30b %30b %30b %30b", in, \
+            $display(`"tag`", $time, ": %h %30b %30b %30b %30b", in, \
                 tag``one_out, tag``two_out, tag``thr_out, tag``fou_out); \
         end \
     end
diff --git a/test/basic/unsigned.sv b/test/basic/unsigned.sv
index 41335e4..6562573 100644
--- a/test/basic/unsigned.sv
+++ b/test/basic/unsigned.sv
@@ -1,6 +1,6 @@
 module top;
     logic [3:0] arr;
-    always_comb
+    initial
         for (int unsigned i = 0; i < 4; i++)
             arr[i] = i;
     initial $display(arr);
diff --git a/test/basic/unsigned.v b/test/basic/unsigned.v
index 62834c5..9d9c2d8 100644
--- a/test/basic/unsigned.v
+++ b/test/basic/unsigned.v
@@ -1,6 +1,6 @@
 module top;
     reg [3:0] arr;
-    always @* begin : block_name
+    initial begin : block_name
         integer i;
         for (i = 0; i < 4; i++)
             arr[i] = i;
diff --git a/test/lex/macro_iv.sv b/test/lex/macro_iv.sv
index 9fc8baa..9abaf2b 100644
--- a/test/lex/macro_iv.sv
+++ b/test/lex/macro_iv.sv
@@ -116,7 +116,7 @@
 
 /* removed MACRO_E because iverlog performs escaping withing normal quotes */
 
-`define MACRO_F(t) $display(`"s t = `\`"t`\`"");
+`define MACRO_F(t) $display(`"s t = `\`"t`\`"`");
 
 module top;
 initial begin