From a5f80e990f53a32560804d630943fa24ab1c6465 Mon Sep 17 00:00:00 2001
From: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Date: Mon, 1 Sep 2025 20:06:47 +0900
Subject: [PATCH] add bufif0

---
 src/Language/SystemVerilog/AST/ModuleItem.hs | 2 ++
 src/Language/SystemVerilog/Parser/Parse.y    | 1 +
 test/basic/gate.sv                           | 4 +++-
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/Language/SystemVerilog/AST/ModuleItem.hs b/src/Language/SystemVerilog/AST/ModuleItem.hs
index 7527cc8..2daf568 100644
--- a/src/Language/SystemVerilog/AST/ModuleItem.hs
+++ b/src/Language/SystemVerilog/AST/ModuleItem.hs
@@ -114,6 +114,7 @@ instance Show AlwaysKW where
 
 data NInputGateKW
     = GateAnd
+    | GateBufif0
     | GateNand
     | GateOr
     | GateNor
@@ -123,6 +124,7 @@ data NInputGateKW
 
 instance Show NInputGateKW where
     show GateAnd  = "and"
+    show GateBufif0  = "bufif0"
     show GateNand = "nand"
     show GateOr   = "or"
     show GateNor  = "nor"
diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index 2fb2475..d0e46af 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -873,6 +873,7 @@ OptGateName :: { (Identifier, [Range]) }
 
 NInputGateKW :: { NInputGateKW }
   : "and"  { GateAnd  }
+  | "bufif0" { GateBufif0 }
   | "nand" { GateNand }
   | "or"   { GateOr   }
   | "nor"  { GateNor  }
diff --git a/test/basic/gate.sv b/test/basic/gate.sv
index 93ae738..2232ad5 100644
--- a/test/basic/gate.sv
+++ b/test/basic/gate.sv
@@ -6,11 +6,13 @@ module top;
     wire output_and_delay;
     wire output_not;
     wire output_buf_delay;
+    wire output_bufif0_delay;
 
     and (output_and, input_a, input_b);
     and #1 (output_and_delay, input_a, input_b);
     not (output_not, input_a);
     buf #2 foo_name (output_buf_delay, input_a);
+    bufif0 (output_bufif0_delay, input_a, input_b);
 
     wire output_nand, output_or, output_nor, output_xor, output_xnor;
     nand (output_nand, input_a, input_b);
@@ -23,7 +25,7 @@ module top;
         $monitor("%3d ", $time,
             input_a, input_b,
             output_and, output_and_delay,
-            output_not, output_buf_delay,
+            output_not, output_buf_delay, output_bufif0_delay,
             output_nand, output_or, output_nor, output_xor, output_xnor);
 
         #1;