From a3937a2719556c3a6f8934a520cd248e8f9a64b4 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Sun, 17 Feb 2019 14:39:33 -0500 Subject: [PATCH] fix preproccessing multi-line defines messing up line numbers --- Language/SystemVerilog/Parser/Preprocess.hs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Language/SystemVerilog/Parser/Preprocess.hs b/Language/SystemVerilog/Parser/Preprocess.hs index e228f19..f0fed29 100644 --- a/Language/SystemVerilog/Parser/Preprocess.hs +++ b/Language/SystemVerilog/Parser/Preprocess.hs @@ -50,7 +50,7 @@ preprocess env file content = unlines $ pp True [] env $ lines $ uncomment file pp _ _ _ [] = [] pp on stack env (a : rest) = if a /= "" && last a == '\\' && head a == '`' - then pp on stack env $ ((init a) ++ " " ++ (head rest)) : (tail rest) + then "" : (pp on stack env $ ((init a) ++ " " ++ (head rest)) : (tail rest)) else case words a of "`define" : name : value -> "" : pp on stack (if on then (name, ppLine env $ unwords value) : env else env) rest "`ifdef" : name : _ -> "" : pp (on && (elem name $ fst $ unzip env)) (on : stack) env rest