From a14d07823066b126835648b3e7d1335081cf7977 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Wed, 11 Sep 2019 22:52:01 -0400 Subject: [PATCH] substitution conversion for size casts (closes #27) --- src/Convert.hs | 4 ++-- src/Convert/Enum.hs | 2 +- src/Convert/{Mux.hs => Simplify.hs} | 27 ++++++++++++++--------- src/Convert/Typedef.hs | 1 + src/Language/SystemVerilog/AST/Expr.hs | 6 ++--- src/Language/SystemVerilog/Parser/Parse.y | 4 ++-- sv2v.cabal | 2 +- test/basic/size_cast.sv | 6 +++++ test/basic/size_cast.v | 6 +++++ 9 files changed, 39 insertions(+), 19 deletions(-) rename src/Convert/{Mux.hs => Simplify.hs} (73%) create mode 100644 test/basic/size_cast.sv create mode 100644 test/basic/size_cast.v diff --git a/src/Convert.hs b/src/Convert.hs index 0eab057..84b2382 100644 --- a/src/Convert.hs +++ b/src/Convert.hs @@ -22,7 +22,6 @@ import qualified Convert.Interface import qualified Convert.IntTypes import qualified Convert.KWArgs import qualified Convert.Logic -import qualified Convert.Mux import qualified Convert.NamedBlock import qualified Convert.NestPI import qualified Convert.Package @@ -30,6 +29,7 @@ import qualified Convert.PackedArray import qualified Convert.ParamType import qualified Convert.RemoveComments import qualified Convert.Return +import qualified Convert.Simplify import qualified Convert.StarPort import qualified Convert.StmtBlock import qualified Convert.Stream @@ -53,9 +53,9 @@ phases excludes = , Convert.EmptyArgs.convert , Convert.IntTypes.convert , Convert.KWArgs.convert - , Convert.Mux.convert , Convert.PackedArray.convert , Convert.ParamType.convert + , Convert.Simplify.convert , Convert.StarPort.convert , Convert.StmtBlock.convert , Convert.Stream.convert diff --git a/src/Convert/Enum.hs b/src/Convert/Enum.hs index 8e300f1..b483005 100644 --- a/src/Convert/Enum.hs +++ b/src/Convert/Enum.hs @@ -95,7 +95,7 @@ toItem ((mr, x), v) = where v' = if mr == Nothing then simplify v - else sizedExpr x r (simplify v) + else sizedExpr x (rangeSize r) (simplify v) rs = maybe [] (\a -> [a]) mr r = defaultRange mr itemType = Implicit Unspecified rs diff --git a/src/Convert/Mux.hs b/src/Convert/Simplify.hs similarity index 73% rename from src/Convert/Mux.hs rename to src/Convert/Simplify.hs index 4a0f393..95149c3 100644 --- a/src/Convert/Mux.hs +++ b/src/Convert/Simplify.hs @@ -1,8 +1,8 @@ {- sv2v - Author: Zachary Snow - - - Elaboration of ternary expressions where the condition references a - - localparam. + - Elaboration of size casts and ternary expressions where the condition + - references a localparam. - - Our conversions generate a lot of ternary expressions. This conversion - attempts to make the code output a bit cleaner. Note that we can only do this @@ -14,7 +14,7 @@ - expression to be simplified further. -} -module Convert.Mux (convert) where +module Convert.Simplify (convert) where import Control.Monad.State import qualified Data.Map.Strict as Map @@ -48,18 +48,25 @@ traverseExprM :: Expr -> State Info Expr traverseExprM = traverseNestedExprsM $ stately convertExpr convertExpr :: Info -> Expr -> Expr +convertExpr info (Cast (Right c) e) = + if sized == e + then Cast (Right c') e + else sized + where + c' = simplify $ traverseNestedExprs (substitute info) (simplify c) + sized = sizedExpr "" c' e convertExpr info (Mux cc aa bb) = if before == after then Mux cc aa bb else simplify $ Mux after aa bb where - before = traverseNestedExprs substitute (simplify cc) + before = traverseNestedExprs (substitute info) (simplify cc) after = simplify before - substitute :: Expr -> Expr - substitute (Ident x) = - case Map.lookup x info of - Nothing -> Ident x - Just e-> e - substitute other = other convertExpr _ other = other +substitute :: Info -> Expr -> Expr +substitute info (Ident x) = + case Map.lookup x info of + Nothing -> Ident x + Just e -> e +substitute _ other = other diff --git a/src/Convert/Typedef.hs b/src/Convert/Typedef.hs index 6656384..9061ddb 100644 --- a/src/Convert/Typedef.hs +++ b/src/Convert/Typedef.hs @@ -57,6 +57,7 @@ convertDescription globalTypes description = else Right $ Ident x convertTypeOrExpr other = other convertExpr :: Expr -> Expr + convertExpr (Cast v e) = Cast (convertTypeOrExpr v) e convertExpr (Bits v) = Bits $ convertTypeOrExpr v convertExpr other = other convertModuleItem :: ModuleItem -> ModuleItem diff --git a/src/Language/SystemVerilog/AST/Expr.hs b/src/Language/SystemVerilog/AST/Expr.hs index 8988d5a..bd9ebe2 100644 --- a/src/Language/SystemVerilog/AST/Expr.hs +++ b/src/Language/SystemVerilog/AST/Expr.hs @@ -217,14 +217,14 @@ endianCondRange r r1 r2 = ) -- attempts to make a number literal have an explicit size -sizedExpr :: Identifier -> Range -> Expr -> Expr -sizedExpr x r (Number n) = +sizedExpr :: Identifier -> Expr -> Expr -> Expr +sizedExpr x s (Number n) = if size /= show resSize then error $ "literal " ++ show n ++ " for " ++ show x ++ " doesn't have size " ++ show size else Number res where - Number size = simplify $ rangeSize r + Number size = simplify s unticked = case n of '\'' : rest -> rest rest -> rest diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y index e833f71..e3eb29f 100644 --- a/src/Language/SystemVerilog/Parser/Parse.y +++ b/src/Language/SystemVerilog/Parser/Parse.y @@ -1021,8 +1021,8 @@ Expr :: { Expr } | Expr "?" Expr ":" Expr { Mux $1 $3 $5 } | CastingType "'" "(" Expr ")" { Cast (Left $1) $4 } | Number "'" "(" Expr ")" { Cast (Right $ Number $1) $4 } - | Identifier "'" "(" Expr ")" { Cast (Left $ Alias (Nothing) $1 []) $4 } - | Identifier "::" Identifier "'" "(" Expr ")" { Cast (Left $ Alias (Just $1) $3 []) $6 } + | Identifier "'" "(" Expr ")" { Cast (Right $ Ident $1 ) $4 } + | Identifier "::" Identifier "'" "(" Expr ")" { Cast (Right $ PSIdent $1 $3) $6 } | Expr "." Identifier { Dot $1 $3 } | "'" "{" PatternItems "}" { Pattern $3 } | "{" StreamOp StreamSize Concat "}" { Stream $2 $3 $4 } diff --git a/sv2v.cabal b/sv2v.cabal index e1eb726..27d7de1 100644 --- a/sv2v.cabal +++ b/sv2v.cabal @@ -66,7 +66,6 @@ executable sv2v Convert.IntTypes Convert.KWArgs Convert.Logic - Convert.Mux Convert.NamedBlock Convert.NestPI Convert.Package @@ -74,6 +73,7 @@ executable sv2v Convert.ParamType Convert.RemoveComments Convert.Return + Convert.Simplify Convert.StarPort Convert.StmtBlock Convert.Stream diff --git a/test/basic/size_cast.sv b/test/basic/size_cast.sv new file mode 100644 index 0000000..a9cd035 --- /dev/null +++ b/test/basic/size_cast.sv @@ -0,0 +1,6 @@ +module top; + localparam BW = 3; + logic [2:0] test; + assign test = BW'(0); + initial $display(test); +endmodule diff --git a/test/basic/size_cast.v b/test/basic/size_cast.v new file mode 100644 index 0000000..c87932b --- /dev/null +++ b/test/basic/size_cast.v @@ -0,0 +1,6 @@ +module top; + localparam BW = 3; + wire [2:0] test; + assign test = 0; + initial $display(test); +endmodule