From 9eceb5567352a030566553a59e3542ae150ad5d6 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Mon, 2 May 2022 14:45:10 -0600 Subject: [PATCH] defer elaboration of void functions --- src/Convert/EmptyArgs.hs | 6 ++++-- src/Convert/FuncRet.hs | 5 ++++- src/Convert/FuncRoutine.hs | 1 + src/Convert/Traverse.hs | 1 + src/Language/SystemVerilog/AST/Type.hs | 3 +++ src/Language/SystemVerilog/Parser/Parse.y | 3 +-- 6 files changed, 14 insertions(+), 5 deletions(-) diff --git a/src/Convert/EmptyArgs.hs b/src/Convert/EmptyArgs.hs index 2710f31..8e9c42a 100644 --- a/src/Convert/EmptyArgs.hs +++ b/src/Convert/EmptyArgs.hs @@ -30,14 +30,16 @@ convertDescription description@Part{} = convertDescription other = other traverseFunctionsM :: ModuleItem -> Writer Idents ModuleItem -traverseFunctionsM (MIPackageItem (Function ml t f decls stmts)) = do +traverseFunctionsM item@(MIPackageItem (Function _ Void _ _ _)) = + return item +traverseFunctionsM (MIPackageItem (Function l t f decls stmts)) = do decls' <- if any isInput decls then return decls else do tell $ Set.singleton f return $ dummyDecl : decls - return $ MIPackageItem $ Function ml t f decls' stmts + return $ MIPackageItem $ Function l t f decls' stmts where dummyType = IntegerVector TReg Unspecified [] dummyDecl = Variable Input dummyType "_sv2v_unused" [] Nil diff --git a/src/Convert/FuncRet.hs b/src/Convert/FuncRet.hs index 350b413..6713ee1 100644 --- a/src/Convert/FuncRet.hs +++ b/src/Convert/FuncRet.hs @@ -1,7 +1,8 @@ {- sv2v - Author: Zachary Snow - - - Conversion which makes function `logic` and `reg` return types implicit + - Conversion which makes function `logic` and `reg` return types implicit and + - converts `void` functions to tasks - - Verilog-2005 restricts function return types to `integer`, `real`, - `realtime`, `time`, and implicit signed/dimensioned types. @@ -16,6 +17,8 @@ convert :: [AST] -> [AST] convert = map $ traverseDescriptions $ traverseModuleItems convertFunction convertFunction :: ModuleItem -> ModuleItem +convertFunction (MIPackageItem (Function ml Void f decls stmts)) = + MIPackageItem $ Task ml f decls stmts convertFunction (MIPackageItem (Function ml t f decls stmts)) = MIPackageItem $ Function ml t' f decls stmts where diff --git a/src/Convert/FuncRoutine.hs b/src/Convert/FuncRoutine.hs index a67bf3b..233458b 100644 --- a/src/Convert/FuncRoutine.hs +++ b/src/Convert/FuncRoutine.hs @@ -32,6 +32,7 @@ convertDescription description@Part{} = convertDescription other = other collectFunctionsM :: ModuleItem -> Writer Idents () +collectFunctionsM (MIPackageItem (Function _ Void _ _ _)) = return () collectFunctionsM (MIPackageItem (Function _ _ f _ _)) = tell $ Set.singleton f collectFunctionsM _ = return () diff --git a/src/Convert/Traverse.hs b/src/Convert/Traverse.hs index b7feb96..68cac0f 100644 --- a/src/Convert/Traverse.hs +++ b/src/Convert/Traverse.hs @@ -834,6 +834,7 @@ traverseSinglyNestedTypesM mapper = tm tm (UnpackedType t r) = do t' <- mapper t return $ UnpackedType t' r + tm Void = return Void traverseSinglyNestedTypes :: Mapper Type -> Mapper Type traverseSinglyNestedTypes = unmonad traverseSinglyNestedTypesM diff --git a/src/Language/SystemVerilog/AST/Type.hs b/src/Language/SystemVerilog/AST/Type.hs index a2ac9fe..b68a1ca 100644 --- a/src/Language/SystemVerilog/AST/Type.hs +++ b/src/Language/SystemVerilog/AST/Type.hs @@ -52,6 +52,7 @@ data Type | TypeOf Expr | TypedefRef Expr | UnpackedType Type [Range] -- used internally + | Void deriving Eq instance Show Type where @@ -74,6 +75,7 @@ instance Show Type where show (TypeOf expr) = printf "type(%s)" (show expr) show (UnpackedType t rs) = printf "UnpackedType(%s, %s)" (show t) (showRanges rs) show (TypedefRef e) = show e + show Void = "void" showFields :: [Field] -> String showFields items = itemsStr @@ -102,6 +104,7 @@ typeRanges typ = NonInteger kw -> (nullRange $ NonInteger kw , []) TypeOf expr -> (nullRange $ TypeOf expr, []) TypedefRef expr -> (nullRange $ TypedefRef expr, []) + Void -> (nullRange Void , []) nullRange :: Type -> ([Range] -> Type) nullRange t [] = t diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y index 5fd454d..c2dbc06 100644 --- a/src/Language/SystemVerilog/Parser/Parse.y +++ b/src/Language/SystemVerilog/Parser/Parse.y @@ -924,7 +924,6 @@ ImportOrExport :: { [PackageItem] } | "export" "*" "::" "*" ";" { [Export "" ""] } TaskOrFunction :: { PackageItem } : "function" Lifetime FuncRetAndName TFItems DeclsAndStmts endfunction StrTag {% checkTag (snd $3) $7 $ Function $2 (fst $3) (snd $3) (map makeInput $4 ++ fst $5) (snd $5) } - | "function" Lifetime "void" Identifier TFItems DeclsAndStmts endfunction StrTag {% checkTag $4 $8 $ Task $2 $4 ($5 ++ fst $6) (snd $6) } | "task" Lifetime Identifier TFItems DeclsAndStmts endtask StrTag {% checkTag $3 $7 $ Task $2 $3 ($4 ++ fst $5) (snd $5) } Typedef :: { Decl } : "typedef" Type Identifier ";" { ParamType Localparam $3 $2 } @@ -965,7 +964,6 @@ OptDPIImportProperty :: { DPIImportProperty } DPITFProto :: { (Type, Identifier, [Decl]) } : "function" FuncRetAndName TFItems { (fst $2 , snd $2, $3) } - | "function" "void" Identifier TFItems { (UnknownType, $3, $4) } | "task" Identifier TFItems { (UnknownType, $2, $3) } Directive :: { String } @@ -995,6 +993,7 @@ FuncRetAndName :: { (Type, Identifier) } | Signing Identifier { (Implicit $1 [], $2) } | DimensionsNonEmpty Identifier { (Implicit Unspecified $1, $2) } | Signing DimensionsNonEmpty Identifier { (Implicit $1 $2, $3) } + | "void" Identifier { (Void , $2) } AlwaysKW :: { AlwaysKW } : "always" { Always }