diff --git a/src/Convert/Foreach.hs b/src/Convert/Foreach.hs index d409d78..458ef99 100644 --- a/src/Convert/Foreach.hs +++ b/src/Convert/Foreach.hs @@ -22,9 +22,9 @@ convertStmt :: Stmt -> Stmt convertStmt (Foreach x idxs stmt) = (foldl (.) id $ map toLoop $ zip [1..] idxs) stmt where - toLoop :: (Int, Maybe Identifier) -> (Stmt -> Stmt) - toLoop (_, Nothing) = id - toLoop (d, Just i) = + toLoop :: (Int, Identifier) -> (Stmt -> Stmt) + toLoop (_, "") = id + toLoop (d, i) = For (Left [idxDecl]) cmp [incr] where queryFn f = DimFn f (Right $ Ident x) (Number $ show d) diff --git a/src/Convert/Traverse.hs b/src/Convert/Traverse.hs index 9dd7655..3dc7b4b 100644 --- a/src/Convert/Traverse.hs +++ b/src/Convert/Traverse.hs @@ -255,14 +255,10 @@ traverseSinglyNestedStmtsM fullMapper = cs traverseAssertionStmtsM :: Monad m => MapperM m Stmt -> MapperM m Assertion traverseAssertionStmtsM mapper = assertionMapper where - actionBlockMapper (ActionBlockIf stmt) = - mapper stmt >>= return . ActionBlockIf - actionBlockMapper (ActionBlockElse Nothing stmt) = - mapper stmt >>= return . ActionBlockElse Nothing - actionBlockMapper (ActionBlockElse (Just s1) s2) = do + actionBlockMapper (ActionBlock s1 s2) = do s1' <- mapper s1 s2' <- mapper s2 - return $ ActionBlockElse (Just s1') s2' + return $ ActionBlock s1' s2' assertionMapper (Assert e ab) = actionBlockMapper ab >>= return . Assert e assertionMapper (Assume e ab) = diff --git a/src/Language/SystemVerilog/AST/ModuleItem.hs b/src/Language/SystemVerilog/AST/ModuleItem.hs index e21d38d..1cf6496 100644 --- a/src/Language/SystemVerilog/AST/ModuleItem.hs +++ b/src/Language/SystemVerilog/AST/ModuleItem.hs @@ -63,10 +63,10 @@ instance Show ModuleItem where showGate kw d x $ show lhs : map show exprs show (NOutputGate kw d x lhss expr) = showGate kw d x $ (map show lhss) ++ [show expr] - show (AssertionItem (mx, a)) = - if mx == Nothing + show (AssertionItem (x, a)) = + if null x then show a - else printf "%s : %s" (fromJust mx) (show a) + else printf "%s : %s" x (show a) show (Instance m params i r ports) = if null params then printf "%s %s%s%s;" m i rStr (showPorts ports) diff --git a/src/Language/SystemVerilog/AST/Stmt.hs b/src/Language/SystemVerilog/AST/Stmt.hs index 4edeafb..31e5c66 100644 --- a/src/Language/SystemVerilog/AST/Stmt.hs +++ b/src/Language/SystemVerilog/AST/Stmt.hs @@ -43,7 +43,7 @@ data Stmt | RepeatL Expr Stmt | DoWhile Expr Stmt | Forever Stmt - | Foreach Identifier [Maybe Identifier] Stmt + | Foreach Identifier [Identifier] Stmt | If ViolationCheck Expr Stmt Stmt | Timing Timing Stmt | Return Expr @@ -79,24 +79,25 @@ instance Show Stmt where showInits (Right asgns) = commas $ map showInit asgns where showInit (l, e) = showAssign (l, AsgnOpEq, e) showAssign :: (LHS, AsgnOp, Expr) -> String - showAssign (l, op, e) = printf "%s %s %s" (show l) (show op) (show e) + showAssign (l, op, e) = (showPad l) ++ (showPad op) ++ (show e) show (Subroutine e a) = printf "%s%s;" (show e) aStr where aStr = if a == Args [] [] then "" else show a - show (Asgn o t v e) = printf "%s %s %s%s;" (show v) (show o) (maybe "" showPad t) (show e) - show (While e s) = printf "while (%s) %s" (show e) (show s) - show (RepeatL e s) = printf "repeat (%s) %s" (show e) (show s) - show (DoWhile e s) = printf "do %s while (%s);" (show s) (show e) - show (Forever s ) = printf "forever %s" (show s) - show (Foreach x i s) = printf "foreach (%s [ %s ]) %s" x (commas $ map (maybe "" id) i) (show s) - show (If u a b Null) = printf "%sif (%s)%s" (showPad u) (show a) (showBranch b) - show (If u a b c ) = printf "%sif (%s)%s\nelse%s" (showPad u) (show a) (showBlockedBranch b) (showElseBranch c) - show (Return e ) = printf "return %s;" (show e) - show (Timing t s ) = printf "%s%s" (show t) (showShortBranch s) - show (Trigger b x) = printf "->%s %s;" (if b then "" else ">") x - show (Assertion a) = show a - show (Continue ) = "continue;" - show (Break ) = "break;" - show (Null ) = ";" + show (Asgn o t v e) = printf "%s %s %s%s;" (show v) (show o) tStr (show e) + where tStr = maybe "" showPad t + show (If u c s Null) = printf "%sif (%s)%s" (showPad u) (show c) (showBranch s) + show (If u c s1 s2 ) = printf "%sif (%s)%s\nelse%s" (showPad u) (show c) (showBlockedBranch s1) (showElseBranch s2) + show (While e s) = printf "while (%s) %s" (show e) (show s) + show (RepeatL e s) = printf "repeat (%s) %s" (show e) (show s) + show (DoWhile e s) = printf "do %s while (%s);" (show s) (show e) + show (Forever s) = printf "forever %s" (show s) + show (Foreach x i s) = printf "foreach (%s [ %s ]) %s" x (commas i) (show s) + show (Return e ) = printf "return %s;" (show e) + show (Timing t s) = printf "%s%s" (show t) (showShortBranch s) + show (Trigger b x) = printf "->%s %s;" (if b then "" else ">") x + show (Assertion a) = show a + show (Continue ) = "continue;" + show (Break ) = "break;" + show (Null ) = ";" show (CommentStmt c) = if elem '\n' c then "// " ++ show c @@ -183,14 +184,12 @@ instance Show Sense where show (SenseStar ) = "*" data ActionBlock - = ActionBlockIf Stmt - | ActionBlockElse (Maybe Stmt) Stmt + = ActionBlock Stmt Stmt deriving Eq instance Show ActionBlock where - show (ActionBlockIf Null ) = ";" - show (ActionBlockIf s ) = printf " %s" (show s) - show (ActionBlockElse Nothing s ) = printf " else %s" (show s) - show (ActionBlockElse (Just s1) s2) = printf " %s else %s" (show s1) (show s2) + show (ActionBlock s Null) = printf " %s" (show s) + show (ActionBlock Null s) = printf " else %s" (show s) + show (ActionBlock s1 s2) = printf " %s else %s" (show s1) (show s2) data PropExpr = PropExpr SeqExpr @@ -228,7 +227,7 @@ instance Show SeqExpr where show (SeqExprDelay me e s) = printf "%s##%s %s" (maybe "" showPad me) (show e) (show s) show (SeqExprFirstMatch e a) = printf "first_match(%s, %s)" (show e) (show a) -type AssertionItem = (Maybe Identifier, Assertion) +type AssertionItem = (Identifier, Assertion) type AssertionExpr = Either PropertySpec Expr data Assertion = Assert AssertionExpr ActionBlock diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y index b11cbb0..3903cd9 100644 --- a/src/Language/SystemVerilog/Parser/Parse.y +++ b/src/Language/SystemVerilog/Parser/Parse.y @@ -690,8 +690,8 @@ ProceduralAssertionStatement :: { Assertion } | ImmediateAssertionStatement { $1 } ConcurrentAssertionItem :: { AssertionItem } - : Identifier ":" ConcurrentAssertionStatement { (Just $1, $3) } - | ConcurrentAssertionStatement { (Nothing, $1) } + : Identifier ":" ConcurrentAssertionStatement { ($1, $3) } + | ConcurrentAssertionStatement { ("", $1) } ConcurrentAssertionStatement :: { Assertion } : "assert" "property" "(" PropertySpec ")" ActionBlock { Assert (Left $4) $6 } | "assume" "property" "(" PropertySpec ")" ActionBlock { Assume (Left $4) $6 } @@ -739,9 +739,9 @@ SeqMatchItem :: { SeqMatchItem } | Identifier CallArgs { Right ($1, $2) } ActionBlock :: { ActionBlock } - : Stmt %prec NoElse { ActionBlockIf $1 } - | "else" Stmt { ActionBlockElse (Nothing) $2 } - | Stmt "else" Stmt { ActionBlockElse (Just $1) $3 } + : Stmt %prec NoElse { ActionBlock $1 Null } + | "else" Stmt { ActionBlock Null $2 } + | Stmt "else" Stmt { ActionBlock $1 $3 } AttributeInstances :: { [Attr] } : {- empty -} { [] } @@ -1029,11 +1029,14 @@ ForStepAssignment :: { (LHS, AsgnOp, Expr) } | IncOrDecOperator LHS { ($2, AsgnOp $1, Number "1") } | LHS IncOrDecOperator { ($1, AsgnOp $2, Number "1") } -IdxVars :: { [Maybe Identifier] } +IdxVars :: { [Identifier] } : "[" IdxVarsInside "]" { $2 } -IdxVarsInside :: { [Maybe Identifier] } - : opt(Identifier) { [$1] } - | opt(Identifier) "," IdxVarsInside { $1 : $3 } +IdxVarsInside :: { [Identifier] } + : IdxVar { [$1] } + | IdxVar "," IdxVarsInside { $1 : $3 } +IdxVar :: { Identifier } + : {- empty -} { "" } + | Identifier { $1 } DeclsAndStmts :: { ([Decl], [Stmt]) } : StmtTrace DeclOrStmt DeclsAndStmts { combineDeclsAndStmts $2 $3 }