diff --git a/CHANGELOG.md b/CHANGELOG.md
index d5242f6..01dada1 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -18,6 +18,7 @@
 * Apply implicit port directions to tasks and functions
 * Support bare delay controls with real number delays
 * Fix parsing of sized ports with implicit directions
+* Ensure arrays used in nested ternary expressions are properly flattened
 
 ## v0.0.8
 
diff --git a/src/Convert/UnpackedArray.hs b/src/Convert/UnpackedArray.hs
index 83846e5..fbe2bf5 100644
--- a/src/Convert/UnpackedArray.hs
+++ b/src/Convert/UnpackedArray.hs
@@ -101,11 +101,6 @@ traverseLHSM :: LHS -> ST LHS
 traverseLHSM x = flatUsageM x >> return x
 
 traverseAsgnM :: (LHS, Expr) -> ST (LHS, Expr)
-traverseAsgnM (x, Mux cond y z) = do
-    flatUsageM x
-    flatUsageM y
-    flatUsageM z
-    return (x, Mux cond y z)
 traverseAsgnM (x, y) = do
     flatUsageM x
     flatUsageM y
@@ -113,6 +108,8 @@ traverseAsgnM (x, y) = do
 
 class ScopeKey t => Key t where
     unbit :: t -> (t, Int)
+    split :: t -> Maybe (t, t)
+    split = const Nothing
 
 instance Key Expr where
     unbit (Bit e _) = (e', n + 1)
@@ -120,6 +117,8 @@ instance Key Expr where
     unbit (Range e _ _) = (e', n)
         where (e', n) = unbit e
     unbit e = (e, 0)
+    split (Mux _ a b) = Just (a, b)
+    split _ = Nothing
 
 instance Key LHS where
     unbit (LHSBit e _) = (e', n + 1)
@@ -132,6 +131,8 @@ instance Key Identifier where
     unbit x = (x, 0)
 
 flatUsageM :: Key k => k -> ST ()
+flatUsageM k | Just (a, b) <- split k =
+    flatUsageM a >> flatUsageM b
 flatUsageM k = do
     let (k', depth) = unbit k
     details <- lookupElemM k'
diff --git a/test/core/array.sv b/test/core/array.sv
index 63ea843..04551a2 100644
--- a/test/core/array.sv
+++ b/test/core/array.sv
@@ -1,3 +1,7 @@
+module mod(input [1:0] x [3]);
+    initial #1 $display("%b %b %b", x[0], x[1], x[2]);
+endmodule
+
 module top;
     logic [1:0] a [3];
     logic [1:0] b [3];
@@ -7,8 +11,20 @@ module top;
     logic [1:0] c [3];
     logic [1:0] d [3];
     logic [1:0] e [3];
+    logic [1:0] f [3];
     initial x = 0;
-    assign c = x ? d : e;
+    assign c = x ? d : !x ? e : f;
+
+    logic [1:0] l [3];
+    logic [1:0] m [3];
+    logic [1:0] n [3];
+    initial begin
+        x = 1;
+        {l[0], l[1], l[2]} = { 2'bXZ, 2'b01, 2'b10 };
+        {m[0], m[1], m[2]} = { 2'b01, 2'b10, 2'b11 };
+        {n[0], n[1], n[2]} = { 2'b10, 2'b00, 2'b10 };
+    end
+    mod mod(!x ? l : x ? m : n);
 
     generate
         begin : A
@@ -16,6 +32,6 @@ module top;
             logic [1:0] d [3];
         end
     endgenerate
-    assign A.d = 0;
+    assign A.d = '{ default: 0 };
     initial $display("%b %b", A.c[0], A.d[0]);
 endmodule
diff --git a/test/core/array.v b/test/core/array.v
index 6943078..fdd56da 100644
--- a/test/core/array.v
+++ b/test/core/array.v
@@ -1,3 +1,7 @@
+module mod(input [5:0] x);
+    initial #1 $display("%b %b %b", x[4+:2], x[2+:2], x[0+:2]);
+endmodule
+
 module top;
     reg [5:0] a;
     wire [5:0] b;
@@ -7,8 +11,20 @@ module top;
     wire [5:0] c;
     wire [5:0] d;
     wire [5:0] e;
+    wire [5:0] f;
     initial x = 0;
-    assign c = x ? d : e;
+    assign c = x ? d : !x ? e : f;
+
+    reg [5:0] l;
+    reg [5:0] m;
+    reg [5:0] n;
+    initial begin
+        x = 1;
+        l = { 2'bXZ, 2'b01, 2'b10 };
+        m = { 2'b01, 2'b10, 2'b11 };
+        n = { 2'b10, 2'b00, 2'b10 };
+    end
+    mod mod(!x ? l : x ? m : n);
 
     generate
         if (1) begin : A