From 988088541255e7afa996dbbf5e66c20d90f2b0f5 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Tue, 8 Oct 2019 22:21:40 -0400 Subject: [PATCH] Revert "allow escaped newline in macro arguments" This reverts commit ba7fbd55065d409d5abd457b775fca021effd480. --- src/Language/SystemVerilog/Parser/Lex.x | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/Language/SystemVerilog/Parser/Lex.x b/src/Language/SystemVerilog/Parser/Lex.x index 224eb4b..b709bc8 100644 --- a/src/Language/SystemVerilog/Parser/Lex.x +++ b/src/Language/SystemVerilog/Parser/Lex.x @@ -780,11 +780,7 @@ takeMacroArguments = do case (stack, ch) of ( s,'\\') -> do ch2 <- takeChar - if ch2 == '\n' - then do - dropWhitespace - loop curr s - else loop (curr ++ [ch, ch2]) s + loop (curr ++ [ch, ch2]) s ([ ], ',') -> return (curr, False) ([ ], ')') -> return (curr, True)