diff --git a/src/Language/SystemVerilog/AST/Stmt.hs b/src/Language/SystemVerilog/AST/Stmt.hs
index bcb1a42..b5e6326 100644
--- a/src/Language/SystemVerilog/AST/Stmt.hs
+++ b/src/Language/SystemVerilog/AST/Stmt.hs
@@ -110,11 +110,11 @@ showBranch stmt = '\n' : (indent $ show stmt)
 showBlockedBranch :: Stmt -> String
 showBlockedBranch stmt =
     showBranch $
-    if isControl
+    if isControl stmt
         then Block Seq "" [] [stmt]
         else stmt
     where
-        isControl = case stmt of
+        isControl s = case s of
             If{} -> True
             For{} -> True
             While{} -> True
@@ -122,6 +122,7 @@ showBlockedBranch stmt =
             DoWhile{} -> True
             Forever{} -> True
             Foreach{} -> True
+            Timing _ subStmt -> isControl subStmt
             _ -> False
 
 showElseBranch :: Stmt -> String
diff --git a/test/basic/else_prec.sv b/test/basic/else_prec.sv
index 0576ef0..bc70259 100644
--- a/test/basic/else_prec.sv
+++ b/test/basic/else_prec.sv
@@ -29,6 +29,18 @@ module top;
                 end
             end
 
+            $display("3 (%b, %b, %b)", a, b, c);
+            if (a) begin
+                #1
+                if (b) begin
+                    $display("FOO");
+                end
+            end else begin
+                if (c) begin
+                    $display("BAR");
+                end
+            end
+
         end
     endtask