From 91e3ac0fb17241374b27bc6bc76d55e47407d905 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Thu, 8 Jul 2021 17:17:45 -0400
Subject: [PATCH] normalize trailing whitespace in escaped identifiers

---
 src/Language/SystemVerilog/Parser/Lex.x |  5 +++++
 test/basic/escaped_identifier.sv        | 14 ++++++++++++++
 2 files changed, 19 insertions(+)
 create mode 100644 test/basic/escaped_identifier.sv

diff --git a/src/Language/SystemVerilog/Parser/Lex.x b/src/Language/SystemVerilog/Parser/Lex.x
index d42ab57..fa5f434 100644
--- a/src/Language/SystemVerilog/Parser/Lex.x
+++ b/src/Language/SystemVerilog/Parser/Lex.x
@@ -498,6 +498,11 @@ postProcess stack (Token Dir_end_keywords _ pos : ts) =
     case stack of
         (_ : stack') -> postProcess stack' ts
         [] -> throwError $ show pos ++ ": unmatched end_keywords"
+postProcess stack (Token Id_escaped str pos : ts) =
+    postProcess stack ts >>= return . (t' :)
+    where
+        t' = Token Id_escaped str' pos
+        str' = (++ " ") $ init str
 postProcess [] (t : ts) = do
     ts' <- postProcess [] ts
     return $ t : ts'
diff --git a/test/basic/escaped_identifier.sv b/test/basic/escaped_identifier.sv
new file mode 100644
index 0000000..9e88d57
--- /dev/null
+++ b/test/basic/escaped_identifier.sv
@@ -0,0 +1,14 @@
+module mod(
+    input \AFancySignalName[3].Something ,
+    output \AFancySignalName[3].SomethingElse
+);
+endmodule
+
+module top;
+    wire \BFancySignalName.Something = 1;
+    wire \BFancySignalName.SomethingElse ;
+    mod inst_of_fancy_module(
+        .\AFancySignalName[3].Something (\BFancySignalName.Something ),
+        .\AFancySignalName[3].SomethingElse (\BFancySignalName.SomethingElse )
+    );
+endmodule