diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index de1f3b2..05a262d 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -419,14 +419,15 @@ DeclOrStmtTokens(delim) :: { [DeclToken] }
   | "<=" opt(DelayOrEventControl) Expr                      delim  { [DTAsgnNBlk $2 $3] }
 DeclOrStmtToken :: { DeclToken }
   : ","            { DTComma }
-  | PartSelect     { DTRange   $1 }
-  | Identifier     { DTIdent   $1 }
-  | Direction      { DTDir     $1 }
-  | "[" Expr "]"   { DTBit     $2 }
-  | "{" LHSs "}"   { DTConcat  $2 }
-  | PartialType    { DTType    $1 }
-  | "." Identifier { DTDot     $2 }
-  | Signing        { DTSigning $1 }
+  | PartSelect     { DTRange    $1 }
+  | Identifier     { DTIdent    $1 }
+  | Direction      { DTDir      $1 }
+  | "[" Expr "]"   { DTBit      $2 }
+  | "{" LHSs "}"   { DTConcat   $2 }
+  | PartialType    { DTType     $1 }
+  | "." Identifier { DTDot      $2 }
+  | Signing        { DTSigning  $1 }
+  | Lifetime       { DTLifetime $1 }
   | Identifier "::" Identifier { DTPSIdent $1 $3 }
 
 VariablePortIdentifiers :: { [(Identifier, Maybe Expr)] }
diff --git a/src/Language/SystemVerilog/Parser/ParseDecl.hs b/src/Language/SystemVerilog/Parser/ParseDecl.hs
index cf3bd5a..ed05852 100644
--- a/src/Language/SystemVerilog/Parser/ParseDecl.hs
+++ b/src/Language/SystemVerilog/Parser/ParseDecl.hs
@@ -22,11 +22,10 @@
  - increasingly convoluted grammars, this became more and more untenable as I
  - added support for more SystemVerilog constructs.
  -
- - Because of how liberal this parser is, the parser will accept some
- - syntactically invalid files. In the future, we may add some basic
- - type-checking to complain about malformed input files. However, we generally
- - assume that users have tested their code with commercial simulator before
- - running it through our tool.
+ - This parser is very liberal, and so accepts some syntactically invalid files.
+ - In the future, we may add some basic type-checking to complain about
+ - malformed input files. However, we generally assume that users have tested
+ - their code with a commercial simulator before running it through our tool.
  -}
 
 module Language.SystemVerilog.Parser.ParseDecl
@@ -60,6 +59,7 @@ data DeclToken
     | DTConcat   [LHS]
     | DTDot      Identifier
     | DTSigning  Signing
+    | DTLifetime Lifetime
     deriving (Show, Eq)
 
 
@@ -263,12 +263,15 @@ parseDTsAsComponents tokens =
 parseDTsAsComponent :: [DeclToken] -> (Component, [DeclToken])
 parseDTsAsComponent [] = error "parseDTsAsComponent unexpected end of tokens"
 parseDTsAsComponent l0 =
-    (component, l4)
+    if l /= Nothing && l /= Just Automatic
+        then error $ "unexpected non-automatic lifetime: " ++ show l0
+        else (component, l5)
     where
-        (dir, l1) = takeDir    l0
-        (tf , l2) = takeType   l1
-        (rs , l3) = takeRanges l2
-        (tps, l4) = takeTrips  l3 True
+        (dir, l1) = takeDir      l0
+        (l  , l2) = takeLifetime l1
+        (tf , l3) = takeType     l2
+        (rs , l4) = takeRanges   l3
+        (tps, l5) = takeTrips    l4 True
         component = (dir, tf rs, tps)
 
 
@@ -312,6 +315,10 @@ takeDir :: [DeclToken] -> (Direction, [DeclToken])
 takeDir (DTDir dir : rest) = (dir  , rest)
 takeDir              rest  = (Local, rest)
 
+takeLifetime :: [DeclToken] -> (Maybe Lifetime, [DeclToken])
+takeLifetime (DTLifetime l : rest) = (Just  l, rest)
+takeLifetime                 rest  = (Nothing, rest)
+
 takeType :: [DeclToken] -> ([Range] -> Type, [DeclToken])
 takeType (DTIdent a  : DTDot b      : rest) = (InterfaceT a (Just b),                       rest)
 takeType (DTType  tf : DTSigning sg : rest) = (tf       sg         ,                        rest)
diff --git a/test/basic/data_lifetime.sv b/test/basic/data_lifetime.sv
new file mode 100644
index 0000000..eae3db5
--- /dev/null
+++ b/test/basic/data_lifetime.sv
@@ -0,0 +1,17 @@
+module top;
+    function automatic logic [31:0] lcg(input logic [31:0] x);
+        automatic logic [3:0] temp;
+        lcg = x;
+        for (temp = 0; temp < 3; temp++) begin
+            lcg *= 1664525;
+            lcg += 1013904223;
+        end
+    endfunction
+
+    initial $display(lcg(0));
+    initial $display(lcg(1));
+    initial $display(lcg(2));
+    initial $display(lcg(3));
+    initial $display(lcg(4));
+    initial $display(lcg(5));
+endmodule
diff --git a/test/basic/data_lifetime.v b/test/basic/data_lifetime.v
new file mode 100644
index 0000000..b2cb687
--- /dev/null
+++ b/test/basic/data_lifetime.v
@@ -0,0 +1,19 @@
+module top;
+    function automatic [31:0] lcg(input [31:0] x);
+    begin : foo
+        reg [3:0] temp;
+        lcg = x;
+        for (temp = 0; temp < 3; temp++) begin
+            lcg *= 1664525;
+            lcg += 1013904223;
+        end
+    end
+    endfunction
+
+    initial $display(lcg(0));
+    initial $display(lcg(1));
+    initial $display(lcg(2));
+    initial $display(lcg(3));
+    initial $display(lcg(4));
+    initial $display(lcg(5));
+endmodule